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llvm-project/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll

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[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP32,M2
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP32,32R1-R5
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP32,32R1-R5
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP32,32R1-R5
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP32,32R1-R5
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP32,32R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,M3
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,GP64,64R6
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,MM,MMR3
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=ALL,MM,MMR6
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
entry:
; ALL-LABEL: lshr_i1:
; ALL: move $2, $4
%r = lshr i1 %a, %b
ret i1 %r
}
define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
entry:
; ALL-LABEL: lshr_i8:
; ALL: srlv $[[T0:[0-9]+]], $4, $5
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; GP32: andi $2, $[[T0]], 255
; GP64: andi $2, $[[T0]], 255
; MM: andi16 $2, $[[T0]], 255
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = lshr i8 %a, %b
ret i8 %r
}
define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
entry:
; ALL-LABEL: lshr_i16:
; ALL: srlv $[[T0:[0-9]+]], $4, $5
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; GP32: andi $2, $[[T0]], 65535
; GP64: andi $2, $[[T0]], 65535
; MM: andi16 $2, $[[T0]], 65535
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = lshr i16 %a, %b
ret i16 %r
}
define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: lshr_i32:
; ALL: srlv $2, $4, $5
%r = lshr i32 %a, %b
ret i32 %r
}
define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: lshr_i64:
; M2: srlv $[[T0:[0-9]+]], $4, $7
; M2: andi $[[T1:[0-9]+]], $7, 32
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; M2: move $3, $[[T0]]
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]]
; M2: addiu $2, $zero, 0
; M2: $[[EXIT:BB[0-9_]+]]:
; M2: jr $ra
; M2: nop
; M2: $[[BB0]]:
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; M2: srlv $[[T2:[0-9]+]], $5, $7
; M2: not $[[T3:[0-9]+]], $7
; M2: sll $[[T4:[0-9]+]], $4, 1
; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
; M2: or $3, $[[T3]], $[[T2]]
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M2: bnez $[[T1]], $[[EXIT:BB[0-9_]+]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; M2: addiu $2, $zero, 0
; M2: $[[BB1]]:
; M2: jr $ra
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M2: move $2, $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
; 32R1-R5: not $[[T1:[0-9]+]], $7
; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; 32R1-R5: or $3, $[[T3]], $[[T0]]
; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
; 32R1-R5: movn $3, $[[T4]], $[[T5]]
; 32R1-R5: jr $ra
; 32R1-R5: movn $2, $zero, $[[T5]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; 32R6: srlv $[[T0:[0-9]+]], $5, $7
; 32R6: not $[[T1:[0-9]+]], $7
; 32R6: sll $[[T2:[0-9]+]], $4, 1
; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]]
; 32R6: andi $[[T5:[0-9]+]], $7, 32
; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]]
; 32R6: srlv $[[T7:[0-9]+]], $4, $7
; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
; 32R6: or $3, $[[T8]], $[[T6]]
; 32R6: jr $ra
; 32R6: seleqz $2, $[[T7]], $[[T5]]
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; GP64: dsrlv $2, $4, $5
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; MMR3: srlv $[[T0:[0-9]+]], $5, $7
[mips] Preparatory work for a generic scheduler Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
2016-08-24 21:00:47 +08:00
; MMR3: not16 $[[T1:[0-9]+]], $7
; MMR3: sll16 $[[T2:[0-9]+]], $4, 1
; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
; MMR3: srlv $[[T5:[0-9]+]], $4, $7
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
[mips] Optimize materialization of i64 constants Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit integer. This allows us to generate the same instructions for the materialization of the same constants regardless the width of their type. Patch by: Vasileios Kalintiris Contributions by: Simon Dardis Reviewers: Daniel Sanders Differential Review: https://reviews.llvm.org/D21689 llvm-svn: 276628
2016-07-25 17:57:28 +08:00
; MMR3: li16 $[[T8:[0-9]+]], 0
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; MMR3: movn $2, $[[T8]], $[[T6]]
; MMR6: srlv $[[T0:[0-9]+]], $5, $7
[mips] Preparatory work for a generic scheduler Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
2016-08-24 21:00:47 +08:00
; MMR6: not16 $[[T1:[0-9]+]], $7
; MMR6: sll16 $[[T2:[0-9]+]], $4, 1
; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]]
; MMR6: srlv $[[T7:[0-9]+]], $4, $7
; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
; MMR6: or $3, $[[T8]], $[[T6]]
; MMR6: seleqz $2, $[[T7]], $[[T5]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = lshr i64 %a, %b
ret i64 %r
}
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: lshr_i128:
[mips] Disable the TImode shift libcalls for 32-bit targets. Summary: The o32 ABI doesn't not support the TImode helpers. For the time being, disable just the shift libcalls as they break recursive builds on MIPS. Reviewers: sdardis Subscribers: llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D24259 llvm-svn: 280798
2016-09-07 18:01:18 +08:00
; o32 shouldn't use TImode helpers.
; GP32-NOT: lw $25, %call16(__lshrti3)($gp)
; MM-NOT: lw $25, %call16(__lshrti3)($2)
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; M3: sll $[[T0:[0-9]+]], $7, 0
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; M3: dsrlv $[[T1:[0-9]+]], $4, $7
[mips] Correct 128-bit shifts on 64-bit targets. Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 llvm-svn: 236099
2015-04-29 20:28:58 +08:00
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; M3: move $3, $[[T1]]
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]]
; M3: daddiu $2, $zero, 0
; M3: [[EXIT:\.LBB[0-9_]+]]:
; M3: jr $ra
; M3: nop
; M3: [[BB0]]:
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]]
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M3: bnez $[[T3]], [[EXIT]]
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; M3: daddiu $2, $zero, 0
[mips] Correct label prefixes for N32 and N64. Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
2016-07-19 18:49:03 +08:00
; M3: [[BB1]]:
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; M3: jr $ra
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
2017-03-16 09:32:29 +08:00
; M3: move $2, $[[T1]]
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrlv $2, $4, $7
[mips] Correct 128-bit shifts on 64-bit targets. Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 llvm-svn: 236099
2015-04-29 20:28:58 +08:00
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $zero, $1
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7
; 64R6: dsll $[[T1:[0-9]+]], $4, 1
; 64R6: sll $[[T2:[0-9]+]], $7, 0
; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
[mips] Correct 128-bit shifts on 64-bit targets. Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 llvm-svn: 236099
2015-04-29 20:28:58 +08:00
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $3, $[[T10]], $[[T8]]
; 64R6: jr $ra
[mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
2015-04-21 18:49:03 +08:00
; 64R6: seleqz $2, $[[T9]], $[[T7]]
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
%r = lshr i128 %a, %b
ret i128 %r
}