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llvm-project/llvm/test/CodeGen/Mips/fp16static.ll

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[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
2015-10-15 22:34:23 +08:00
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16
Make sure we call externals from libraries properly when -static. For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
2013-02-07 12:34:51 +08:00
@x = common global float 0.000000e+00, align 4
define void @foo() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load float, float* @x, align 4
%1 = load float, float* @x, align 4
Make sure we call externals from libraries properly when -static. For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
2013-02-07 12:34:51 +08:00
%mul = fmul float %0, %1
store float %mul, float* @x, align 4
; CHECK-STATIC16: jal __mips16_mulsf3
ret void
}