2017-05-26 05:26:32 +08:00
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# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
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# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
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2017-03-28 04:46:37 +08:00
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# REQUIRES: asserts
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--- |
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; ModuleID = 'foo.ll'
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source_filename = "foo.ll"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "arm---eabi"
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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; Function Attrs: nounwind
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define <8 x i8> @foo(i8* %A) {
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%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 1
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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ret <8 x i8> %tmp4
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}
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declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32)
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# CHECK: ********** MI Scheduling **********
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# CHECK: ScheduleDAGMILive::schedule starting
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# CHECK: SU(1): %vreg1<def> = VLD4d8Pseudo %vreg0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0
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# CHECK: Latency : 8
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# CHECK: Single Issue : true;
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# CHECK: SU(2): %vreg4<def> = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:%noreg; DPR:%vreg4 QQPR:%vreg1
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# CHECK: Latency : 5
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# CHECK: Single Issue : false;
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# CHECK: SU(3): %vreg5<def>, %vreg6<def> = VMOVRRD %vreg4, pred:14, pred:%noreg; GPR:%vreg5,%vreg6 DPR:%vreg4
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# CHECK: Latency : 4
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# CHECK: Single Issue : false;
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# TOPDOWN: Scheduling SU(1) %vreg1<def> = VLD4d8Pseudo
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# TOPDOWN: Bump cycle to end group
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# TOPDOWN: Scheduling SU(2) %vreg4<def> = VADDv8i8
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# BOTTOMUP: Scheduling SU(2) %vreg4<def> = VADDv8i8
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# BOTTOMUP: Scheduling SU(1) %vreg1<def> = VLD4d8Pseudo
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# BOTTOMUP: Bump cycle to begin group
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...
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---
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name: foo
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: qqpr }
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- { id: 2, class: dpr }
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- { id: 3, class: dpr }
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- { id: 4, class: dpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0 (%ir-block.0):
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liveins: %r0
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%0 = COPY %r0
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%1 = VLD4d8Pseudo %0, 8, 14, _ :: (load 32 from %ir.A, align 8)
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%4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, _
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%5, %6 = VMOVRRD %4, 14, _
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%r0 = COPY %5
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%r1 = COPY %6
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BX_RET 14, _, implicit %r0, implicit killed %r1
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...
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