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llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c

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[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
[RISCV][NFC] Fix RVV intrinsic tests. 1. Skip the temporary file 2. Test cc1 with -S to verify codegen work well. Add '-target-feature +m' because the backend requires it to calculate the vscaled size/offset. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D99082
2021-03-22 23:20:48 +08:00
// REQUIRES: riscv-registered-target
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
[RISCV][Clang] Update new overloading rules for RVV intrinsics. RVV intrinsics has new overloading rule, please see https://github.com/riscv/rvv-intrinsic-doc/commit/82aac7dad4c6c1c351ed5b17ca6007c395843ed7 Changed: 1. Rename `generic` to `overloaded` because the new rule is not using C11 generic. 2. Change HasGeneric to HasNoMaskedOverloaded because all masked operations support overloading api. 3. Add more overloaded tests due to overloading rule changed. Differential Revision: https://reviews.llvm.org/D99189
2021-03-22 22:51:52 +08:00
#include <riscv_vector.h>
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16mf4_t test_vfadd_vv_f16mf4 (vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16mf4_t test_vfadd_vf_f16mf4 (vfloat16mf4_t op1, _Float16 op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16mf2_t test_vfadd_vv_f16mf2 (vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16mf2_t test_vfadd_vf_f16mf2 (vfloat16mf2_t op1, _Float16 op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m1_t test_vfadd_vv_f16m1 (vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m1_t test_vfadd_vf_f16m1 (vfloat16m1_t op1, _Float16 op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m2_t test_vfadd_vv_f16m2 (vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m2_t test_vfadd_vf_f16m2 (vfloat16m2_t op1, _Float16 op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m4_t test_vfadd_vv_f16m4 (vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m4_t test_vfadd_vf_f16m4 (vfloat16m4_t op1, _Float16 op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m8_t test_vfadd_vv_f16m8 (vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfadd.nxv32f16.f16.i64(<vscale x 32 x half> [[OP1:%.*]], half [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat16m8_t test_vfadd_vf_f16m8 (vfloat16m8_t op1, _Float16 op2, size_t vl) {
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
return vfadd(op1, op2, vl);
}
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f32mf2(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32mf2_t test_vfadd_vv_f32mf2 (vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f32mf2(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfadd.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.*]], float [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32mf2_t test_vfadd_vf_f32mf2 (vfloat32mf2_t op1, float op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m1(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m1_t test_vfadd_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m1(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.f32.i64(<vscale x 2 x float> [[OP1:%.*]], float [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m1_t test_vfadd_vf_f32m1 (vfloat32m1_t op1, float op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m2(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m2_t test_vfadd_vv_f32m2 (vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m2(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.f32.i64(<vscale x 4 x float> [[OP1:%.*]], float [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m2_t test_vfadd_vf_f32m2 (vfloat32m2_t op1, float op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m4(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m4_t test_vfadd_vv_f32m4 (vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m4(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfadd.nxv8f32.f32.i64(<vscale x 8 x float> [[OP1:%.*]], float [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m4_t test_vfadd_vf_f32m4 (vfloat32m4_t op1, float op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m8(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m8_t test_vfadd_vv_f32m8 (vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m8(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfadd.nxv16f32.f32.i64(<vscale x 16 x float> [[OP1:%.*]], float [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat32m8_t test_vfadd_vf_f32m8 (vfloat32m8_t op1, float op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m1(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m1_t test_vfadd_vv_f64m1 (vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m1(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.f64.i64(<vscale x 1 x double> [[OP1:%.*]], double [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m1_t test_vfadd_vf_f64m1 (vfloat64m1_t op1, double op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m2(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m2_t test_vfadd_vv_f64m2 (vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m2(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfadd.nxv2f64.f64.i64(<vscale x 2 x double> [[OP1:%.*]], double [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m2_t test_vfadd_vf_f64m2 (vfloat64m2_t op1, double op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m4(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m4_t test_vfadd_vv_f64m4 (vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m4(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.f64.i64(<vscale x 4 x double> [[OP1:%.*]], double [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m4_t test_vfadd_vf_f64m4 (vfloat64m4_t op1, double op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m8(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
2021-10-03 15:43:38 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m8_t test_vfadd_vv_f64m8 (vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m8(
// CHECK-RV64-NEXT: entry:
[RISCV] Apply clang_builtin_alias to overloaded builtins. We only apply `clang_builtin_alias` to non-masked builtins. Masked builtins could not use `clang_builtin_alias` because the operand order is different between overloaded intrinsics and builtins. A bunch of test cases need to be updated. Differential Revision: https://reviews.llvm.org/D100658
2021-04-16 23:39:08 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfadd.nxv8f64.f64.i64(<vscale x 8 x double> [[OP1:%.*]], double [[OP2:%.*]], i64 [[VL:%.*]])
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] Define _m intrinsics as builtins, instead of macros." This reverts commit 97f0c63783f52389bd8842df205379ceade7a89d. As discussed in https://reviews.llvm.org/D110684, it increased the compile time and the binary size of clang more than 1%. I reverted this patch first to think about a better way to do it.
2021-10-13 11:42:38 +08:00
vfloat64m8_t test_vfadd_vf_f64m8 (vfloat64m8_t op1, double op2, size_t vl) {
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
return vfadd(op1, op2, vl);
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16mf4_t test_vfadd_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf4_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16mf4_t test_vfadd_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf2_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16mf2_t test_vfadd_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f16mf2_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16mf2_t test_vfadd_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m1_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m1_t test_vfadd_vv_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m1_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m1_t test_vfadd_vf_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m2_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m2_t test_vfadd_vv_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m2_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m2_t test_vfadd_vf_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m4_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m4_t test_vfadd_vv_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m4_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m4_t test_vfadd_vf_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f16m8_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m8_t test_vfadd_vv_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f16m8_m(
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat16m8_t test_vfadd_vf_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Support half-precision floating point for RVV intrinsics. Use _Float16 as the half-precision floating point type. Define a new type specifier 'x' for the _Float16 type. Differential Revision: https://reviews.llvm.org/D105001
2021-06-28 13:38:41 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f32mf2_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32mf2_t test_vfadd_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f32mf2_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32mf2_t test_vfadd_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m1_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m1_t test_vfadd_vv_f32m1_m (vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m1_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m1_t test_vfadd_vf_f32m1_m (vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m2_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m2_t test_vfadd_vv_f32m2_m (vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m2_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m2_t test_vfadd_vf_f32m2_m (vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m4_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m4_t test_vfadd_vv_f32m4_m (vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m4_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m4_t test_vfadd_vf_f32m4_m (vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f32m8_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m8_t test_vfadd_vv_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f32m8_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat32m8_t test_vfadd_vf_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, float op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m1_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m1_t test_vfadd_vv_f64m1_m (vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m1_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m1_t test_vfadd_vf_f64m1_m (vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, double op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m2_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m2_t test_vfadd_vv_f64m2_m (vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m2_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m2_t test_vfadd_vf_f64m2_m (vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, double op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m4_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m4_t test_vfadd_vv_f64m4_m (vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m4_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m4_t test_vfadd_vf_f64m4_m (vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, double op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vv_f64m8_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m8_t test_vfadd_vv_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
// CHECK-RV64-LABEL: @test_vfadd_vf_f64m8_m(
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: entry:
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR. Previous patch only reverts C builtins for tail policy. In order to keep LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 14:35:56 +08:00
//
Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics." This reverts commit 7afa61e71877a5b7892ffe4992f804cd84807240.
2021-10-13 14:50:45 +08:00
vfloat64m8_t test_vfadd_vf_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
return vfadd(mask, maskedoff, op1, op2, vl);
[Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. Demonstrate how to generate vadd/vfadd intrinsic functions 1. add -gen-riscv-vector-builtins for clang builtins. 2. add -gen-riscv-vector-builtin-codegen for clang codegen. 3. add -gen-riscv-vector-header for riscv_vector.h. It also generates ifdef directives with extension checking, base on D94403. 4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h. Generate overloading version Header for generic api. https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface 5. update tblgen doc for riscv related options. riscv_vector.td also defines some unused type transformers for vadd, because I think it could demonstrate how tranfer type work and we need them for the whole intrinsic functions implementation in the future. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D95016
2021-03-05 23:40:28 +08:00
}