2017-10-28 02:32:23 +08:00
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// RUN: %clang_cc1 -triple i686-linux-gnu -target-cpu i686 -emit-llvm %s -o - | FileCheck %s
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2015-06-12 09:35:52 +08:00
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int baz(int a) { return 4; }
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int __attribute__((target("avx,sse4.2,arch=ivybridge"))) foo(int a) { return 4; }
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2015-06-12 09:35:56 +08:00
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int __attribute__((target("tune=sandybridge"))) walrus(int a) { return 4; }
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2015-06-12 09:36:00 +08:00
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int __attribute__((target("fpmath=387"))) koala(int a) { return 4; }
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2015-06-12 09:35:56 +08:00
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2015-08-28 04:05:48 +08:00
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int __attribute__((target("no-sse2"))) echidna(int a) { return 4; }
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2015-06-12 09:35:58 +08:00
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2015-07-01 08:08:32 +08:00
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int __attribute__((target("sse4"))) panda(int a) { return 4; }
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2017-10-27 01:54:22 +08:00
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int __attribute__((target("no-sse4"))) narwhal(int a) { return 4; }
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2015-07-01 08:08:32 +08:00
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2015-06-12 09:35:52 +08:00
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int bar(int a) { return baz(a) + foo(a); }
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2015-07-07 07:51:59 +08:00
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int __attribute__((target("avx, sse4.2, arch= ivybridge"))) qux(int a) { return 4; }
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2015-08-28 04:05:48 +08:00
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int __attribute__((target("no-aes, arch=ivybridge"))) qax(int a) { return 4; }
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2015-07-07 07:51:59 +08:00
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Handle sse turning on mmx, but no -mmx not turning off SSE.
Rationale :
// sse3
__m128d test_mm_addsub_pd(__m128d A, __m128d B) {
return _mm_addsub_pd(A, B);
}
// mmx
void shift(__m64 a, __m64 b, int c) {
_mm_slli_pi16(a, c);
_mm_slli_pi32(a, c);
_mm_slli_si64(a, c);
_mm_srli_pi16(a, c);
_mm_srli_pi32(a, c);
_mm_srli_si64(a, c);
_mm_srai_pi16(a, c);
_mm_srai_pi32(a, c);
}
clang -msse3 -mno-mmx file.c -c
For this code we should be able to explicitly turn off MMX
without affecting the compilation of the SSE3 function and then
diagnose and error on compiling the MMX function.
This is a preparatory patch to the actual diagnosis code which is
coming in a future patch. This sets us up to have the correct information
where we need it and verifies that it's being emitted for the backend
to handle.
llvm-svn: 249733
2015-10-09 04:10:18 +08:00
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int __attribute__((target("no-mmx"))) qq(int a) { return 40; }
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2017-10-28 02:32:23 +08:00
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int __attribute__((target("arch=lakemont,mmx"))) lake(int a) { return 4; }
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2016-04-05 23:04:26 +08:00
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2018-02-13 01:01:41 +08:00
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int use_before_def(void);
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int useage(void){
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return use_before_def();
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}
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// Adding the attribute to a definition does update it in IR.
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int __attribute__((target("arch=lakemont,mmx"))) use_before_def(void) {
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return 5;
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}
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2015-06-12 09:35:52 +08:00
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// Check that we emit the additional subtarget and cpu features for foo and not for baz or bar.
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// CHECK: baz{{.*}} #0
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// CHECK: foo{{.*}} #1
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2015-06-12 09:35:56 +08:00
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// We ignore the tune attribute so walrus should be identical to baz and bar.
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// CHECK: walrus{{.*}} #0
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2015-06-12 09:36:00 +08:00
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// We're currently ignoring the fpmath attribute so koala should be identical to baz and bar.
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// CHECK: koala{{.*}} #0
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2015-06-12 09:35:58 +08:00
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// CHECK: echidna{{.*}} #2
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2015-08-29 10:59:37 +08:00
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// CHECK: panda{{.*}} #3
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2017-10-27 01:54:22 +08:00
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// CHECK: narwhal{{.*}} #4
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2015-06-12 09:35:52 +08:00
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// CHECK: bar{{.*}} #0
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2015-07-07 07:51:59 +08:00
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// CHECK: qux{{.*}} #1
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2017-10-27 01:54:22 +08:00
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// CHECK: qax{{.*}} #5
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// CHECK: qq{{.*}} #6
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// CHECK: lake{{.*}} #7
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2018-02-13 01:01:41 +08:00
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// CHECK: use_before_def{{.*}} #7
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2017-10-28 02:32:23 +08:00
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// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+x87"
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2018-09-11 05:57:53 +08:00
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// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
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[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
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2017-10-28 02:32:23 +08:00
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// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
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[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
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2018-02-18 05:04:35 +08:00
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// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
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2017-10-28 02:32:23 +08:00
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// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-3dnow,-3dnowa,-mmx"
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// CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+mmx"
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