2016-05-10 17:09:20 +08:00
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; RUN: llc < %s -O1 -march=sparc | FileCheck %s -check-prefix=NO_ITIN
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; RUN: llc < %s -O1 -march=sparc -mcpu=leon2 | FileCheck %s -check-prefix=LEON2_ITIN
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; RUN: llc < %s -O1 -march=sparc -mcpu=leon3 | FileCheck %s -check-prefix=LEON3_4_ITIN
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; RUN: llc < %s -O1 -march=sparc -mcpu=leon4 | FileCheck %s -check-prefix=LEON3_4_ITIN
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; NO_ITIN-LABEL: f32_ops:
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; NO_ITIN: ld
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; NO_ITIN-NEXT: ld
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; NO_ITIN-NEXT: ld
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; NO_ITIN-NEXT: ld
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; NO_ITIN-NEXT: fadds
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; NO_ITIN-NEXT: fsubs
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; NO_ITIN-NEXT: fmuls
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; NO_ITIN-NEXT: retl
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; NO_ITIN-NEXT: fdivs
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; LEON2_ITIN-LABEL: f32_ops:
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; LEON2_ITIN: ld
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; LEON2_ITIN-NEXT: ld
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; LEON2_ITIN-NEXT: fadds
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; LEON2_ITIN-NEXT: ld
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; LEON2_ITIN-NEXT: fsubs
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; LEON2_ITIN-NEXT: ld
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; LEON2_ITIN-NEXT: fmuls
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; LEON2_ITIN-NEXT: retl
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; LEON2_ITIN-NEXT: fdivs
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; LEON3_4_ITIN-LABEL: f32_ops:
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; LEON3_4_ITIN: ld
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; LEON3_4_ITIN-NEXT: ld
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; LEON3_4_ITIN-NEXT: ld
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2017-05-18 04:18:13 +08:00
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; LEON3_4_ITIN-NEXT: fadds
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Add LiveRangeShrink pass to shrink live range within BB.
Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB.
Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb
Reviewed By: MatzeB, andreadb
Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D32563
llvm-svn: 302938
2017-05-13 03:29:27 +08:00
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; LEON3_4_ITIN-NEXT: ld
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2016-05-10 17:09:20 +08:00
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; LEON3_4_ITIN-NEXT: fsubs
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; LEON3_4_ITIN-NEXT: fmuls
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; LEON3_4_ITIN-NEXT: retl
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; LEON3_4_ITIN-NEXT: fdivs
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define float @f32_ops(float* byval %a, float* byval %b, float* byval %c, float* byval %d) {
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entry:
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%0 = load float, float* %a, align 8
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%1 = load float, float* %b, align 8
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%2 = load float, float* %c, align 8
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%3 = load float, float* %d, align 8
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%4 = fadd float %0, %1
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%5 = fsub float %4, %2
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%6 = fmul float %5, %3
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%7 = fdiv float %6, %4
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ret float %7
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2017-12-01 00:12:24 +08:00
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}
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