[FPEnv] Constrained FCmp intrinsics
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
2019-12-06 18:30:04 +08:00
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; Test that floating-point instructions that set cc are *not* used to
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; eliminate *strict* compares for load complement, load negative and load
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; positive
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Load complement (sign-bit flipped).
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; Test f32
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define float @f1(float %a, float %b, float %f) #0 {
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; CHECK-LABEL: f1:
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; CHECK: ltebr
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; CHECK-NEXT: ber %r14
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%neg = fneg float %f
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%cond = call i1 @llvm.experimental.constrained.fcmp.f32(
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float %neg, float 0.0,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, float %a, float %b
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ret float %res
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}
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; Test f64
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define double @f2(double %a, double %b, double %f) #0 {
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; CHECK-LABEL: f2:
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; CHECK: ltdbr
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; CHECK-NEXT: ber %r14
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%neg = fneg double %f
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%cond = call i1 @llvm.experimental.constrained.fcmp.f64(
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double %neg, double 0.0,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Negation of floating-point absolute.
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; Test f32
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declare float @llvm.fabs.f32(float %f)
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define float @f3(float %a, float %b, float %f) #0 {
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; CHECK-LABEL: f3:
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; CHECK: ltebr
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; CHECK-NEXT: ber %r14
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2020-05-30 00:17:23 +08:00
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%abs = call float @llvm.fabs.f32(float %f) #0
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[FPEnv] Constrained FCmp intrinsics
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
2019-12-06 18:30:04 +08:00
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%neg = fneg float %abs
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%cond = call i1 @llvm.experimental.constrained.fcmp.f32(
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float %neg, float 0.0,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, float %a, float %b
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ret float %res
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}
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; Test f64
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declare double @llvm.fabs.f64(double %f)
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define double @f4(double %a, double %b, double %f) #0 {
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; CHECK-LABEL: f4:
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; CHECK: ltdbr
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; CHECK-NEXT: ber %r14
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2020-05-30 00:17:23 +08:00
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%abs = call double @llvm.fabs.f64(double %f) #0
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[FPEnv] Constrained FCmp intrinsics
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
2019-12-06 18:30:04 +08:00
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%neg = fneg double %abs
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%cond = call i1 @llvm.experimental.constrained.fcmp.f64(
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double %neg, double 0.0,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Absolute floating-point value.
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; Test f32
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define float @f5(float %a, float %b, float %f) #0 {
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; CHECK-LABEL: f5:
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; CHECK: ltebr
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; CHECK-NEXT: ber %r14
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2020-05-30 00:17:23 +08:00
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%abs = call float @llvm.fabs.f32(float %f) #0
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[FPEnv] Constrained FCmp intrinsics
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
2019-12-06 18:30:04 +08:00
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%cond = call i1 @llvm.experimental.constrained.fcmp.f32(
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float %abs, float 0.0,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, float %a, float %b
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ret float %res
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}
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; Test f64
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define double @f6(double %a, double %b, double %f) #0 {
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; CHECK-LABEL: f6:
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; CHECK: ltdbr
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; CHECK-NEXT: ber %r14
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2020-05-30 00:17:23 +08:00
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%abs = call double @llvm.fabs.f64(double %f) #0
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[FPEnv] Constrained FCmp intrinsics
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
2019-12-06 18:30:04 +08:00
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%cond = call i1 @llvm.experimental.constrained.fcmp.f64(
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double %abs, double 0.0,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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attributes #0 = { strictfp }
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declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
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