forked from OSchip/llvm-project
99 lines
3.8 KiB
LLVM
99 lines
3.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; If we have some pattern that leaves only some low bits set, and then performs
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; left-shift of those bits, we can combine those two shifts into a shift+mask.
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; There are many variants to this pattern:
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; c) (x & (-1 >> maskNbits)) << shiftNbits
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; simplify to:
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; (x << shiftNbits) & (-1 >> ((-(maskNbits+shiftNbits))+32))
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; Simple tests.
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declare void @use32(i32)
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define i32 @t0_basic(i32 %x, i32 %nbits) {
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; CHECK-LABEL: @t0_basic(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = lshr i32 -1, %nbits
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%t1 = and i32 %t0, %x
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%t2 = add i32 %nbits, -1
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call void @use32(i32 %t0)
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call void @use32(i32 %t2)
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%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
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ret i32 %t3
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}
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; Vectors
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declare void @use8xi32(<8 x i32>)
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define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[T0:%.*]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and <8 x i32> [[T0]], [[X:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = shl <8 x i32> [[T1]], [[T2]]
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; CHECK-NEXT: ret <8 x i32> [[T3]]
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;
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%t0 = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
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%t1 = and <8 x i32> %t0, %x
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%t2 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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call void @use8xi32(<8 x i32> %t0)
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call void @use8xi32(<8 x i32> %t2)
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%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
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ret <8 x i32> %t3
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}
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define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t1_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and <8 x i32> [[T0]], [[X:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = shl <8 x i32> [[T1]], [[T2]]
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; CHECK-NEXT: ret <8 x i32> [[T3]]
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;
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%t0 = lshr <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
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%t1 = and <8 x i32> %t0, %x
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%t2 = add <8 x i32> %nbits, <i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32, i32 33>
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call void @use8xi32(<8 x i32> %t0)
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call void @use8xi32(<8 x i32> %t2)
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%t3 = shl <8 x i32> %t1, %t2 ; shift is smaller than mask
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ret <8 x i32> %t3
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}
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; Extra uses.
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define i32 @n3_extrause(i32 %x, i32 %nbits) {
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; CHECK-LABEL: @n3_extrause(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t0 = lshr i32 -1, %nbits
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%t1 = and i32 %t0, %x
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%t2 = add i32 %nbits, -1
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call void @use32(i32 %t0)
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call void @use32(i32 %t1) ; BAD
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call void @use32(i32 %t2)
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%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
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ret i32 %t3
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}
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