maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/RISCV/arith-with-overflow.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

85 lines
2.5 KiB
LLVM
Raw Normal View History

[RISCV] Add tests for overflow intrinsics This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
2018-06-19 14:45:47 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: sadd:
; RV32I: # %bb.0: # %entry
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: addi a3, zero, -1
; RV32I-NEXT: slt a4, a3, a1
; RV32I-NEXT: slt a5, a3, a0
; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: slt a0, a3, a1
; RV32I-NEXT: xor a0, a5, a0
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: and a0, a4, a0
; RV32I-NEXT: sw a1, 0(a2)
[RISCV] Add tests for overflow intrinsics This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
2018-06-19 14:45:47 +08:00
; RV32I-NEXT: ret
entry:
%x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c
ret i1 %ovf
}
define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: ssub:
; RV32I: # %bb.0: # %entry
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: addi a3, zero, -1
; RV32I-NEXT: slt a4, a3, a1
; RV32I-NEXT: slt a5, a3, a0
; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: snez a4, a4
; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: slt a0, a3, a1
; RV32I-NEXT: xor a0, a5, a0
[RISCV] Add tests for overflow intrinsics This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
2018-06-19 14:45:47 +08:00
; RV32I-NEXT: snez a0, a0
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: and a0, a4, a0
; RV32I-NEXT: sw a1, 0(a2)
[RISCV] Add tests for overflow intrinsics This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
2018-06-19 14:45:47 +08:00
; RV32I-NEXT: ret
entry:
%x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c
ret i1 %ovf
}
define i1 @uadd(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: uadd:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: add a1, a0, a1
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-NEXT: sltu a0, a1, a0
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a1, 0(a2)
[RISCV] Add tests for overflow intrinsics This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
2018-06-19 14:45:47 +08:00
; RV32I-NEXT: ret
entry:
%x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c
ret i1 %ovf
}
define i1 @usub(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: usub:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: sub a1, a0, a1
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-NEXT: sltu a0, a0, a1
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a1, 0(a2)
[RISCV] Add tests for overflow intrinsics This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
2018-06-19 14:45:47 +08:00
; RV32I-NEXT: ret
entry:
%x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%calc = extractvalue {i32, i1} %x, 0
%ovf = extractvalue {i32, i1} %x, 1
store i32 %calc, i32* %c
ret i1 %ovf
}