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llvm-project/llvm/test/CodeGen/ARM/msr-it-block.ll

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[ARM] MSR instructions implicitly set CPSR The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
2016-06-08 23:26:34 +08:00
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=V6M --check-prefix=CHECK
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=V7M --check-prefix=CHECK
; RUN: llc < %s -mtriple=thumbv7a-none-eabi | FileCheck %s --check-prefix=V7A --check-prefix=CHECK
; RUN: llc < %s -mtriple=armv7a-none-eabi | FileCheck %s --check-prefix=V7A --check-prefix=CHECK
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7a-arm-none-eabi"
define void @test_const(i32 %val) {
; CHECK-LABEL: test_const:
entry:
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %write_reg, label %exit
write_reg:
tail call void @llvm.write_register.i32(metadata !0, i32 0)
tail call void @llvm.write_register.i32(metadata !0, i32 0)
; V6M: msr apsr, {{r[0-9]+}}
; V6M: msr apsr, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
[ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic In the encoding of system registers in the M-class MSR instruction the mask bits should be 2 for registers that don't take a _<bits> qualifier (the instruction is unpredictable otherwise), and should also be 2 if the register takes a _<bits> qualifier but it's not present as no _<bits> is an alias for _nzcvq. Differential Revision: https://reviews.llvm.org/D29828 llvm-svn: 294762
2017-02-11 01:41:08 +08:00
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
[ARM] MSR instructions implicitly set CPSR The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
2016-06-08 23:26:34 +08:00
br label %exit
exit:
ret void
}
define void @test_var(i32 %val, i32 %apsr) {
; CHECK-LABEL: test_var:
entry:
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %write_reg, label %exit
write_reg:
tail call void @llvm.write_register.i32(metadata !0, i32 %apsr)
tail call void @llvm.write_register.i32(metadata !0, i32 %apsr)
; V6M: msr apsr, {{r[0-9]+}}
; V6M: msr apsr, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
; V7M: msr apsr_nzcvq, {{r[0-9]+}}
[ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic In the encoding of system registers in the M-class MSR instruction the mask bits should be 2 for registers that don't take a _<bits> qualifier (the instruction is unpredictable otherwise), and should also be 2 if the register takes a _<bits> qualifier but it's not present as no _<bits> is an alias for _nzcvq. Differential Revision: https://reviews.llvm.org/D29828 llvm-svn: 294762
2017-02-11 01:41:08 +08:00
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
; V7A: msr APSR_nzcvq, {{r[0-9]+}}
[ARM] MSR instructions implicitly set CPSR The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
2016-06-08 23:26:34 +08:00
br label %exit
exit:
ret void
}
declare void @llvm.write_register.i32(metadata, i32)
!0 = !{!"apsr"}