forked from OSchip/llvm-project
35 lines
1.5 KiB
Plaintext
35 lines
1.5 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# Check that when we jump through several subregisters in sequence of
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# reg_sequence we can still find a plain src for a copy.
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# In this specific test, we want %4 to read directly from %1 and
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# %5 from %0. These values come from the respective chains:
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# %4 -> %3.sub0 -> %2.sub1 -> %1
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# %5 -> %3.sub1 -> %2.sub0 -> %0
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#
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# We used to not simplify this because we were bailing when two
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# subreg indices were in the same chain (%3.subX and %2.subY)
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---
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name: reg_sequence_removal
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: reg_sequence_removal
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[REG_SEQUENCE]].sub1, %subreg.sub0, [[REG_SEQUENCE]].sub0, %subreg.sub1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
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; GCN: KILL [[COPY3]], implicit [[COPY2]]
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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%3:vreg_64 = REG_SEQUENCE %2.sub1, %subreg.sub0, %2.sub0, %subreg.sub1
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%4:vgpr_32 = COPY %3.sub0
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%5:vgpr_32 = COPY %3.sub1
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KILL implicit %4, %5
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...
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