2017-07-22 06:37:03 +08:00
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//===--- X86.cpp - Implement X86 target feature support -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements X86 TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "clang/Basic/Builtins.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/TargetBuiltins.h"
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2018-02-09 07:15:02 +08:00
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#include "llvm/ADT/StringExtras.h"
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2017-07-22 06:37:03 +08:00
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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Implement Attribute Target MultiVersioning
GCC's attribute 'target', in addition to being an optimization hint,
also allows function multiversioning. We currently have the former
implemented, this is the latter's implementation.
This works by enabling functions with the same name/signature to coexist,
so that they can all be emitted. Multiversion state is stored in the
FunctionDecl itself, and SemaDecl manages the definitions.
Note that it ends up having to permit redefinition of functions so
that they can all be emitted. Additionally, all versions of the function
must be emitted, so this also manages that.
Note that this includes some additional rules that GCC does not, since
defining something as a MultiVersion function after a usage has been made illegal.
The only 'history rewriting' that happens is if a function is emitted before
it has been converted to a multiversion'ed function, at which point its name
needs to be changed.
Function templates and virtual functions are NOT yet supported (not supported
in GCC either).
Additionally, constructors/destructors are disallowed, but the former is
planned.
llvm-svn: 322028
2018-01-09 05:34:17 +08:00
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#include "llvm/Support/TargetParser.h"
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2017-07-22 06:37:03 +08:00
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namespace clang {
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namespace targets {
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const Builtin::Info BuiltinInfoX86[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
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{#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
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#include "clang/Basic/BuiltinsX86.def"
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
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{#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
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#include "clang/Basic/BuiltinsX86_64.def"
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};
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static const char *const GCCRegNames[] = {
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"ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
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"st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
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"argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
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"xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
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"mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
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"r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
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"xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
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"ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
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"ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
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"xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
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"xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
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"ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
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"ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
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"zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
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"zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
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"zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
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"zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
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"k2", "k3", "k4", "k5", "k6", "k7",
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2017-07-30 18:19:10 +08:00
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"cr0", "cr2", "cr3", "cr4", "cr8",
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2017-08-01 18:51:09 +08:00
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"dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
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2017-11-21 16:50:10 +08:00
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"bnd0", "bnd1", "bnd2", "bnd3",
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2017-07-22 06:37:03 +08:00
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};
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const TargetInfo::AddlRegName AddlRegNames[] = {
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{{"al", "ah", "eax", "rax"}, 0},
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{{"bl", "bh", "ebx", "rbx"}, 3},
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{{"cl", "ch", "ecx", "rcx"}, 2},
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{{"dl", "dh", "edx", "rdx"}, 1},
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{{"esi", "rsi"}, 4},
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{{"edi", "rdi"}, 5},
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{{"esp", "rsp"}, 7},
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{{"ebp", "rbp"}, 6},
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{{"r8d", "r8w", "r8b"}, 38},
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{{"r9d", "r9w", "r9b"}, 39},
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{{"r10d", "r10w", "r10b"}, 40},
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{{"r11d", "r11w", "r11b"}, 41},
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{{"r12d", "r12w", "r12b"}, 42},
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{{"r13d", "r13w", "r13b"}, 43},
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{{"r14d", "r14w", "r14b"}, 44},
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{{"r15d", "r15w", "r15b"}, 45},
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};
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} // namespace targets
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} // namespace clang
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using namespace clang;
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using namespace clang::targets;
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bool X86TargetInfo::setFPMath(StringRef Name) {
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if (Name == "387") {
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FPMath = FP_387;
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return true;
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}
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if (Name == "sse") {
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FPMath = FP_SSE;
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return true;
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}
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return false;
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}
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2018-01-09 16:53:59 +08:00
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bool X86TargetInfo::checkCFProtectionReturnSupported(
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DiagnosticsEngine &Diags) const {
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if (HasSHSTK)
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return true;
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Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return"
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<< "-mshstk";
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return false;
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}
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bool X86TargetInfo::checkCFProtectionBranchSupported(
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DiagnosticsEngine &Diags) const {
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if (HasIBT)
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return true;
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Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch"
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<< "-mibt";
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return false;
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}
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2017-07-22 06:37:03 +08:00
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bool X86TargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
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// FIXME: This *really* should not be here.
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// X86_64 always has SSE2.
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if (getTriple().getArch() == llvm::Triple::x86_64)
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setFeatureEnabledImpl(Features, "sse2", true);
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const CPUKind Kind = getCPUKind(CPU);
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// Enable X87 for all X86 processors but Lakemont.
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if (Kind != CK_Lakemont)
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setFeatureEnabledImpl(Features, "x87", true);
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switch (Kind) {
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case CK_Generic:
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case CK_i386:
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case CK_i486:
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case CK_i586:
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case CK_Pentium:
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case CK_PentiumPro:
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case CK_Lakemont:
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break;
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2017-09-18 03:05:46 +08:00
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2017-07-22 06:37:03 +08:00
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case CK_PentiumMMX:
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case CK_Pentium2:
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case CK_K6:
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case CK_WinChipC6:
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setFeatureEnabledImpl(Features, "mmx", true);
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break;
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2017-09-18 03:05:46 +08:00
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2017-11-19 10:55:15 +08:00
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case CK_Icelake:
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2017-12-27 16:16:54 +08:00
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setFeatureEnabledImpl(Features, "vaes", true);
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2017-12-27 16:37:47 +08:00
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setFeatureEnabledImpl(Features, "gfni", true);
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2017-12-27 17:00:31 +08:00
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setFeatureEnabledImpl(Features, "vpclmulqdq", true);
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2017-12-27 18:01:00 +08:00
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setFeatureEnabledImpl(Features, "avx512bitalg", true);
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2017-12-27 18:37:51 +08:00
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setFeatureEnabledImpl(Features, "avx512vnni", true);
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[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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setFeatureEnabledImpl(Features, "avx512vbmi2", true);
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2017-12-28 06:25:59 +08:00
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setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
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2018-01-21 02:36:52 +08:00
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setFeatureEnabledImpl(Features, "rdpid", true);
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2017-11-19 10:55:15 +08:00
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LLVM_FALLTHROUGH;
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2017-07-22 06:37:03 +08:00
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case CK_Cannonlake:
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setFeatureEnabledImpl(Features, "avx512ifma", true);
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setFeatureEnabledImpl(Features, "avx512vbmi", true);
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setFeatureEnabledImpl(Features, "sha", true);
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LLVM_FALLTHROUGH;
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case CK_SkylakeServer:
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setFeatureEnabledImpl(Features, "avx512f", true);
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setFeatureEnabledImpl(Features, "avx512cd", true);
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setFeatureEnabledImpl(Features, "avx512dq", true);
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setFeatureEnabledImpl(Features, "avx512bw", true);
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setFeatureEnabledImpl(Features, "avx512vl", true);
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2017-12-29 14:39:16 +08:00
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setFeatureEnabledImpl(Features, "pku", true);
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setFeatureEnabledImpl(Features, "clwb", true);
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2017-07-22 06:37:03 +08:00
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LLVM_FALLTHROUGH;
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case CK_SkylakeClient:
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setFeatureEnabledImpl(Features, "xsavec", true);
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setFeatureEnabledImpl(Features, "xsaves", true);
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setFeatureEnabledImpl(Features, "mpx", true);
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setFeatureEnabledImpl(Features, "sgx", true);
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setFeatureEnabledImpl(Features, "clflushopt", true);
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setFeatureEnabledImpl(Features, "rtm", true);
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LLVM_FALLTHROUGH;
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case CK_Broadwell:
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setFeatureEnabledImpl(Features, "rdseed", true);
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setFeatureEnabledImpl(Features, "adx", true);
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2017-12-22 12:51:00 +08:00
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setFeatureEnabledImpl(Features, "prfchw", true);
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2017-07-22 06:37:03 +08:00
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LLVM_FALLTHROUGH;
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case CK_Haswell:
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setFeatureEnabledImpl(Features, "avx2", true);
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setFeatureEnabledImpl(Features, "lzcnt", true);
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setFeatureEnabledImpl(Features, "bmi", true);
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setFeatureEnabledImpl(Features, "bmi2", true);
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setFeatureEnabledImpl(Features, "fma", true);
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setFeatureEnabledImpl(Features, "movbe", true);
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LLVM_FALLTHROUGH;
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case CK_IvyBridge:
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setFeatureEnabledImpl(Features, "rdrnd", true);
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setFeatureEnabledImpl(Features, "f16c", true);
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setFeatureEnabledImpl(Features, "fsgsbase", true);
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LLVM_FALLTHROUGH;
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case CK_SandyBridge:
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setFeatureEnabledImpl(Features, "avx", true);
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setFeatureEnabledImpl(Features, "xsave", true);
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setFeatureEnabledImpl(Features, "xsaveopt", true);
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LLVM_FALLTHROUGH;
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case CK_Westmere:
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setFeatureEnabledImpl(Features, "aes", true);
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setFeatureEnabledImpl(Features, "pclmul", true);
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LLVM_FALLTHROUGH;
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case CK_Nehalem:
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setFeatureEnabledImpl(Features, "sse4.2", true);
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2017-09-18 03:05:46 +08:00
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LLVM_FALLTHROUGH;
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case CK_Penryn:
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setFeatureEnabledImpl(Features, "sse4.1", true);
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LLVM_FALLTHROUGH;
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case CK_Core2:
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setFeatureEnabledImpl(Features, "ssse3", true);
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LLVM_FALLTHROUGH;
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case CK_Yonah:
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case CK_Prescott:
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case CK_Nocona:
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setFeatureEnabledImpl(Features, "sse3", true);
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2017-07-22 06:37:03 +08:00
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setFeatureEnabledImpl(Features, "cx16", true);
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2017-09-18 03:05:46 +08:00
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LLVM_FALLTHROUGH;
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case CK_PentiumM:
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case CK_Pentium4:
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case CK_x86_64:
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setFeatureEnabledImpl(Features, "sse2", true);
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LLVM_FALLTHROUGH;
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case CK_Pentium3:
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case CK_C3_2:
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setFeatureEnabledImpl(Features, "sse", true);
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setFeatureEnabledImpl(Features, "fxsr", true);
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2017-07-22 06:37:03 +08:00
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break;
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2017-09-18 03:05:46 +08:00
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2017-07-22 06:37:03 +08:00
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case CK_Goldmont:
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setFeatureEnabledImpl(Features, "sha", true);
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setFeatureEnabledImpl(Features, "rdseed", true);
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setFeatureEnabledImpl(Features, "xsave", true);
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setFeatureEnabledImpl(Features, "xsaveopt", true);
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setFeatureEnabledImpl(Features, "xsavec", true);
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setFeatureEnabledImpl(Features, "xsaves", true);
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setFeatureEnabledImpl(Features, "clflushopt", true);
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setFeatureEnabledImpl(Features, "mpx", true);
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2017-09-25 21:49:32 +08:00
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|
|
setFeatureEnabledImpl(Features, "fsgsbase", true);
|
2017-07-22 06:37:03 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_Silvermont:
|
2018-01-27 03:34:45 +08:00
|
|
|
setFeatureEnabledImpl(Features, "rdrnd", true);
|
2017-07-22 06:37:03 +08:00
|
|
|
setFeatureEnabledImpl(Features, "aes", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "pclmul", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse4.2", true);
|
2017-12-22 12:51:00 +08:00
|
|
|
setFeatureEnabledImpl(Features, "prfchw", true);
|
2017-07-22 06:37:03 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_Bonnell:
|
|
|
|
|
setFeatureEnabledImpl(Features, "movbe", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "ssse3", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fxsr", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "cx16", true);
|
|
|
|
|
break;
|
2017-09-18 03:05:46 +08:00
|
|
|
|
2017-10-14 02:14:24 +08:00
|
|
|
case CK_KNM:
|
|
|
|
|
// TODO: Add avx5124fmaps/avx5124vnniw.
|
2017-10-26 01:10:58 +08:00
|
|
|
setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_KNL:
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx512f", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx512cd", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx512er", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx512pf", true);
|
2017-12-22 12:51:00 +08:00
|
|
|
setFeatureEnabledImpl(Features, "prfchw", true);
|
2017-07-22 06:37:03 +08:00
|
|
|
setFeatureEnabledImpl(Features, "prefetchwt1", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fxsr", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "rdseed", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "adx", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "lzcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi2", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "rtm", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fma", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "rdrnd", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "f16c", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fsgsbase", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "aes", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "pclmul", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "cx16", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsaveopt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsave", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "movbe", true);
|
|
|
|
|
break;
|
2017-09-18 03:05:46 +08:00
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_K6_2:
|
|
|
|
|
case CK_K6_3:
|
|
|
|
|
case CK_WinChip2:
|
|
|
|
|
case CK_C3:
|
|
|
|
|
setFeatureEnabledImpl(Features, "3dnow", true);
|
|
|
|
|
break;
|
2017-09-18 03:05:46 +08:00
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_AMDFAM10:
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse4a", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "lzcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "popcnt", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_K8SSE3:
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse3", true);
|
2017-09-18 03:05:46 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_K8:
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse2", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_AthlonXP:
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse", true);
|
2017-07-22 06:37:03 +08:00
|
|
|
setFeatureEnabledImpl(Features, "fxsr", true);
|
2017-09-18 03:05:46 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_Athlon:
|
|
|
|
|
case CK_Geode:
|
|
|
|
|
setFeatureEnabledImpl(Features, "3dnowa", true);
|
2017-07-22 06:37:03 +08:00
|
|
|
break;
|
2017-09-18 03:05:46 +08:00
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_BTVER2:
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "aes", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "pclmul", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "f16c", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsaveopt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "movbe", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_BTVER1:
|
|
|
|
|
setFeatureEnabledImpl(Features, "ssse3", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse4a", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "lzcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "popcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "prfchw", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "cx16", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fxsr", true);
|
|
|
|
|
break;
|
2017-09-18 03:05:46 +08:00
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_ZNVER1:
|
|
|
|
|
setFeatureEnabledImpl(Features, "adx", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "aes", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx2", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi2", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "clflushopt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "clzero", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "cx16", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "f16c", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fma", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fsgsbase", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fxsr", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "lzcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "mwaitx", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "movbe", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "pclmul", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "popcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "prfchw", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "rdrnd", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "rdseed", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "sha", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "sse4a", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsave", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsavec", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsaveopt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsaves", true);
|
|
|
|
|
break;
|
2017-09-18 03:05:46 +08:00
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_BDVER4:
|
|
|
|
|
setFeatureEnabledImpl(Features, "avx2", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi2", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "mwaitx", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_BDVER3:
|
|
|
|
|
setFeatureEnabledImpl(Features, "fsgsbase", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsaveopt", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_BDVER2:
|
|
|
|
|
setFeatureEnabledImpl(Features, "bmi", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fma", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "f16c", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "tbm", true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_BDVER1:
|
|
|
|
|
// xop implies avx, sse4a and fma4.
|
|
|
|
|
setFeatureEnabledImpl(Features, "xop", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "lwp", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "lzcnt", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "aes", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "pclmul", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "prfchw", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "cx16", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "fxsr", true);
|
|
|
|
|
setFeatureEnabledImpl(Features, "xsave", true);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
// Can't do this earlier because we need to be able to explicitly enable
|
|
|
|
|
// or disable these features and the things that they depend upon.
|
|
|
|
|
|
|
|
|
|
// Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
|
|
|
|
|
auto I = Features.find("sse4.2");
|
|
|
|
|
if (I != Features.end() && I->getValue() &&
|
|
|
|
|
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
|
|
|
|
|
FeaturesVec.end())
|
|
|
|
|
Features["popcnt"] = true;
|
|
|
|
|
|
|
|
|
|
// Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
|
|
|
|
|
I = Features.find("3dnow");
|
|
|
|
|
if (I != Features.end() && I->getValue() &&
|
|
|
|
|
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
|
|
|
|
|
FeaturesVec.end())
|
|
|
|
|
Features["prfchw"] = true;
|
|
|
|
|
|
|
|
|
|
// Additionally, if SSE is enabled and mmx is not explicitly disabled,
|
|
|
|
|
// then enable MMX.
|
|
|
|
|
I = Features.find("sse");
|
|
|
|
|
if (I != Features.end() && I->getValue() &&
|
|
|
|
|
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
|
|
|
|
|
FeaturesVec.end())
|
|
|
|
|
Features["mmx"] = true;
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
|
|
|
|
|
X86SSEEnum Level, bool Enabled) {
|
|
|
|
|
if (Enabled) {
|
|
|
|
|
switch (Level) {
|
|
|
|
|
case AVX512F:
|
2018-01-11 09:37:59 +08:00
|
|
|
Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX2:
|
|
|
|
|
Features["avx2"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX:
|
|
|
|
|
Features["avx"] = true;
|
|
|
|
|
Features["xsave"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE42:
|
|
|
|
|
Features["sse4.2"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE41:
|
|
|
|
|
Features["sse4.1"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSSE3:
|
|
|
|
|
Features["ssse3"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE3:
|
|
|
|
|
Features["sse3"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE2:
|
|
|
|
|
Features["sse2"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE1:
|
|
|
|
|
Features["sse"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case NoSSE:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (Level) {
|
|
|
|
|
case NoSSE:
|
|
|
|
|
case SSE1:
|
|
|
|
|
Features["sse"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE2:
|
|
|
|
|
Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
|
2017-12-27 16:37:47 +08:00
|
|
|
Features["gfni"] = false;
|
2017-07-22 06:37:03 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE3:
|
|
|
|
|
Features["sse3"] = false;
|
|
|
|
|
setXOPLevel(Features, NoXOP, false);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSSE3:
|
|
|
|
|
Features["ssse3"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE41:
|
|
|
|
|
Features["sse4.1"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE42:
|
|
|
|
|
Features["sse4.2"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX:
|
|
|
|
|
Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
|
2017-12-27 17:00:31 +08:00
|
|
|
Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
|
2017-07-22 06:37:03 +08:00
|
|
|
setXOPLevel(Features, FMA4, false);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX2:
|
|
|
|
|
Features["avx2"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX512F:
|
|
|
|
|
Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
|
|
|
|
|
Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
|
|
|
|
|
Features["avx512vl"] = Features["avx512vbmi"] =
|
2017-12-27 18:01:00 +08:00
|
|
|
Features["avx512ifma"] = Features["avx512vpopcntdq"] =
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
Features["avx512bitalg"] = Features["avx512vnni"] =
|
|
|
|
|
Features["avx512vbmi2"] = false;
|
2017-07-22 06:37:03 +08:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
|
|
|
|
|
MMX3DNowEnum Level, bool Enabled) {
|
|
|
|
|
if (Enabled) {
|
|
|
|
|
switch (Level) {
|
|
|
|
|
case AMD3DNowAthlon:
|
|
|
|
|
Features["3dnowa"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AMD3DNow:
|
|
|
|
|
Features["3dnow"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case MMX:
|
|
|
|
|
Features["mmx"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case NoMMX3DNow:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (Level) {
|
|
|
|
|
case NoMMX3DNow:
|
|
|
|
|
case MMX:
|
|
|
|
|
Features["mmx"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AMD3DNow:
|
|
|
|
|
Features["3dnow"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AMD3DNowAthlon:
|
|
|
|
|
Features["3dnowa"] = false;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
|
|
|
|
|
bool Enabled) {
|
|
|
|
|
if (Enabled) {
|
|
|
|
|
switch (Level) {
|
|
|
|
|
case XOP:
|
|
|
|
|
Features["xop"] = true;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case FMA4:
|
|
|
|
|
Features["fma4"] = true;
|
|
|
|
|
setSSELevel(Features, AVX, true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE4A:
|
|
|
|
|
Features["sse4a"] = true;
|
|
|
|
|
setSSELevel(Features, SSE3, true);
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case NoXOP:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (Level) {
|
|
|
|
|
case NoXOP:
|
|
|
|
|
case SSE4A:
|
|
|
|
|
Features["sse4a"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case FMA4:
|
|
|
|
|
Features["fma4"] = false;
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case XOP:
|
|
|
|
|
Features["xop"] = false;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
|
|
|
|
|
StringRef Name, bool Enabled) {
|
|
|
|
|
// This is a bit of a hack to deal with the sse4 target feature when used
|
|
|
|
|
// as part of the target attribute. We handle sse4 correctly everywhere
|
|
|
|
|
// else. See below for more information on how we handle the sse4 options.
|
|
|
|
|
if (Name != "sse4")
|
|
|
|
|
Features[Name] = Enabled;
|
|
|
|
|
|
|
|
|
|
if (Name == "mmx") {
|
|
|
|
|
setMMXLevel(Features, MMX, Enabled);
|
|
|
|
|
} else if (Name == "sse") {
|
|
|
|
|
setSSELevel(Features, SSE1, Enabled);
|
|
|
|
|
} else if (Name == "sse2") {
|
|
|
|
|
setSSELevel(Features, SSE2, Enabled);
|
|
|
|
|
} else if (Name == "sse3") {
|
|
|
|
|
setSSELevel(Features, SSE3, Enabled);
|
|
|
|
|
} else if (Name == "ssse3") {
|
|
|
|
|
setSSELevel(Features, SSSE3, Enabled);
|
|
|
|
|
} else if (Name == "sse4.2") {
|
|
|
|
|
setSSELevel(Features, SSE42, Enabled);
|
|
|
|
|
} else if (Name == "sse4.1") {
|
|
|
|
|
setSSELevel(Features, SSE41, Enabled);
|
|
|
|
|
} else if (Name == "3dnow") {
|
|
|
|
|
setMMXLevel(Features, AMD3DNow, Enabled);
|
|
|
|
|
} else if (Name == "3dnowa") {
|
|
|
|
|
setMMXLevel(Features, AMD3DNowAthlon, Enabled);
|
|
|
|
|
} else if (Name == "aes") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, SSE2, Enabled);
|
2017-12-27 16:16:54 +08:00
|
|
|
else
|
|
|
|
|
Features["vaes"] = false;
|
|
|
|
|
} else if (Name == "vaes") {
|
|
|
|
|
if (Enabled) {
|
|
|
|
|
setSSELevel(Features, AVX, Enabled);
|
|
|
|
|
Features["aes"] = true;
|
|
|
|
|
}
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Name == "pclmul") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, SSE2, Enabled);
|
2017-12-27 17:00:31 +08:00
|
|
|
else
|
|
|
|
|
Features["vpclmulqdq"] = false;
|
|
|
|
|
} else if (Name == "vpclmulqdq") {
|
|
|
|
|
if (Enabled) {
|
|
|
|
|
setSSELevel(Features, AVX, Enabled);
|
|
|
|
|
Features["pclmul"] = true;
|
|
|
|
|
}
|
2017-12-27 16:37:47 +08:00
|
|
|
} else if (Name == "gfni") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, SSE2, Enabled);
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Name == "avx") {
|
|
|
|
|
setSSELevel(Features, AVX, Enabled);
|
|
|
|
|
} else if (Name == "avx2") {
|
|
|
|
|
setSSELevel(Features, AVX2, Enabled);
|
|
|
|
|
} else if (Name == "avx512f") {
|
|
|
|
|
setSSELevel(Features, AVX512F, Enabled);
|
|
|
|
|
} else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
|
|
|
|
|
Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
|
|
|
|
|
Name == "avx512vbmi" || Name == "avx512ifma" ||
|
2017-12-27 18:37:51 +08:00
|
|
|
Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
Name == "avx512vnni" || Name == "avx512vbmi2") {
|
2017-07-22 06:37:03 +08:00
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, AVX512F, Enabled);
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
// Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
|
|
|
|
|
if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
|
2017-07-22 06:37:03 +08:00
|
|
|
Features["avx512bw"] = true;
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
// Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
|
2017-07-22 06:37:03 +08:00
|
|
|
if (Name == "avx512bw" && !Enabled)
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
Features["avx512vbmi"] = Features["avx512vbmi2"] =
|
|
|
|
|
Features["avx512bitalg"] = false;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Name == "fma") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, AVX, Enabled);
|
2018-01-11 09:37:59 +08:00
|
|
|
else
|
|
|
|
|
setSSELevel(Features, AVX512F, Enabled);
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Name == "fma4") {
|
|
|
|
|
setXOPLevel(Features, FMA4, Enabled);
|
|
|
|
|
} else if (Name == "xop") {
|
|
|
|
|
setXOPLevel(Features, XOP, Enabled);
|
|
|
|
|
} else if (Name == "sse4a") {
|
|
|
|
|
setXOPLevel(Features, SSE4A, Enabled);
|
|
|
|
|
} else if (Name == "f16c") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, AVX, Enabled);
|
2018-01-11 09:37:59 +08:00
|
|
|
else
|
|
|
|
|
setSSELevel(Features, AVX512F, Enabled);
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Name == "sha") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, SSE2, Enabled);
|
|
|
|
|
} else if (Name == "sse4") {
|
|
|
|
|
// We can get here via the __target__ attribute since that's not controlled
|
|
|
|
|
// via the -msse4/-mno-sse4 command line alias. Handle this the same way
|
|
|
|
|
// here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
|
|
|
|
|
// disabled.
|
|
|
|
|
if (Enabled)
|
|
|
|
|
setSSELevel(Features, SSE42, Enabled);
|
|
|
|
|
else
|
|
|
|
|
setSSELevel(Features, SSE41, Enabled);
|
|
|
|
|
} else if (Name == "xsave") {
|
|
|
|
|
if (!Enabled)
|
|
|
|
|
Features["xsaveopt"] = false;
|
|
|
|
|
} else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
|
|
|
|
|
if (Enabled)
|
|
|
|
|
Features["xsave"] = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// handleTargetFeatures - Perform initialization based on the user
|
|
|
|
|
/// configured set of features.
|
|
|
|
|
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
|
|
|
|
|
DiagnosticsEngine &Diags) {
|
|
|
|
|
for (const auto &Feature : Features) {
|
|
|
|
|
if (Feature[0] != '+')
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (Feature == "+aes") {
|
|
|
|
|
HasAES = true;
|
2017-12-27 16:16:54 +08:00
|
|
|
} else if (Feature == "+vaes") {
|
|
|
|
|
HasVAES = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+pclmul") {
|
|
|
|
|
HasPCLMUL = true;
|
2017-12-27 17:00:31 +08:00
|
|
|
} else if (Feature == "+vpclmulqdq") {
|
|
|
|
|
HasVPCLMULQDQ = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+lzcnt") {
|
|
|
|
|
HasLZCNT = true;
|
|
|
|
|
} else if (Feature == "+rdrnd") {
|
|
|
|
|
HasRDRND = true;
|
|
|
|
|
} else if (Feature == "+fsgsbase") {
|
|
|
|
|
HasFSGSBASE = true;
|
|
|
|
|
} else if (Feature == "+bmi") {
|
|
|
|
|
HasBMI = true;
|
|
|
|
|
} else if (Feature == "+bmi2") {
|
|
|
|
|
HasBMI2 = true;
|
|
|
|
|
} else if (Feature == "+popcnt") {
|
|
|
|
|
HasPOPCNT = true;
|
|
|
|
|
} else if (Feature == "+rtm") {
|
|
|
|
|
HasRTM = true;
|
|
|
|
|
} else if (Feature == "+prfchw") {
|
|
|
|
|
HasPRFCHW = true;
|
|
|
|
|
} else if (Feature == "+rdseed") {
|
|
|
|
|
HasRDSEED = true;
|
|
|
|
|
} else if (Feature == "+adx") {
|
|
|
|
|
HasADX = true;
|
|
|
|
|
} else if (Feature == "+tbm") {
|
|
|
|
|
HasTBM = true;
|
|
|
|
|
} else if (Feature == "+lwp") {
|
|
|
|
|
HasLWP = true;
|
|
|
|
|
} else if (Feature == "+fma") {
|
|
|
|
|
HasFMA = true;
|
|
|
|
|
} else if (Feature == "+f16c") {
|
|
|
|
|
HasF16C = true;
|
2017-12-27 16:37:47 +08:00
|
|
|
} else if (Feature == "+gfni") {
|
|
|
|
|
HasGFNI = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+avx512cd") {
|
|
|
|
|
HasAVX512CD = true;
|
|
|
|
|
} else if (Feature == "+avx512vpopcntdq") {
|
|
|
|
|
HasAVX512VPOPCNTDQ = true;
|
2017-12-27 18:37:51 +08:00
|
|
|
} else if (Feature == "+avx512vnni") {
|
|
|
|
|
HasAVX512VNNI = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+avx512er") {
|
|
|
|
|
HasAVX512ER = true;
|
|
|
|
|
} else if (Feature == "+avx512pf") {
|
|
|
|
|
HasAVX512PF = true;
|
|
|
|
|
} else if (Feature == "+avx512dq") {
|
|
|
|
|
HasAVX512DQ = true;
|
2017-12-27 18:01:00 +08:00
|
|
|
} else if (Feature == "+avx512bitalg") {
|
|
|
|
|
HasAVX512BITALG = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+avx512bw") {
|
|
|
|
|
HasAVX512BW = true;
|
|
|
|
|
} else if (Feature == "+avx512vl") {
|
|
|
|
|
HasAVX512VL = true;
|
|
|
|
|
} else if (Feature == "+avx512vbmi") {
|
|
|
|
|
HasAVX512VBMI = true;
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
} else if (Feature == "+avx512vbmi2") {
|
|
|
|
|
HasAVX512VBMI2 = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+avx512ifma") {
|
|
|
|
|
HasAVX512IFMA = true;
|
|
|
|
|
} else if (Feature == "+sha") {
|
|
|
|
|
HasSHA = true;
|
|
|
|
|
} else if (Feature == "+mpx") {
|
|
|
|
|
HasMPX = true;
|
2017-11-26 20:34:54 +08:00
|
|
|
} else if (Feature == "+shstk") {
|
|
|
|
|
HasSHSTK = true;
|
|
|
|
|
} else if (Feature == "+ibt") {
|
|
|
|
|
HasIBT = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
} else if (Feature == "+movbe") {
|
|
|
|
|
HasMOVBE = true;
|
|
|
|
|
} else if (Feature == "+sgx") {
|
|
|
|
|
HasSGX = true;
|
|
|
|
|
} else if (Feature == "+cx16") {
|
|
|
|
|
HasCX16 = true;
|
|
|
|
|
} else if (Feature == "+fxsr") {
|
|
|
|
|
HasFXSR = true;
|
|
|
|
|
} else if (Feature == "+xsave") {
|
|
|
|
|
HasXSAVE = true;
|
|
|
|
|
} else if (Feature == "+xsaveopt") {
|
|
|
|
|
HasXSAVEOPT = true;
|
|
|
|
|
} else if (Feature == "+xsavec") {
|
|
|
|
|
HasXSAVEC = true;
|
|
|
|
|
} else if (Feature == "+xsaves") {
|
|
|
|
|
HasXSAVES = true;
|
|
|
|
|
} else if (Feature == "+mwaitx") {
|
|
|
|
|
HasMWAITX = true;
|
|
|
|
|
} else if (Feature == "+pku") {
|
|
|
|
|
HasPKU = true;
|
|
|
|
|
} else if (Feature == "+clflushopt") {
|
|
|
|
|
HasCLFLUSHOPT = true;
|
|
|
|
|
} else if (Feature == "+clwb") {
|
|
|
|
|
HasCLWB = true;
|
|
|
|
|
} else if (Feature == "+prefetchwt1") {
|
|
|
|
|
HasPREFETCHWT1 = true;
|
|
|
|
|
} else if (Feature == "+clzero") {
|
|
|
|
|
HasCLZERO = true;
|
2018-01-21 02:36:52 +08:00
|
|
|
} else if (Feature == "+rdpid") {
|
|
|
|
|
HasRDPID = true;
|
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
|
|
|
} else if (Feature == "+retpoline") {
|
|
|
|
|
HasRetpoline = true;
|
|
|
|
|
} else if (Feature == "+retpoline-external-thunk") {
|
|
|
|
|
HasRetpolineExternalThunk = true;
|
2017-07-22 06:37:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
|
|
|
|
|
.Case("+avx512f", AVX512F)
|
|
|
|
|
.Case("+avx2", AVX2)
|
|
|
|
|
.Case("+avx", AVX)
|
|
|
|
|
.Case("+sse4.2", SSE42)
|
|
|
|
|
.Case("+sse4.1", SSE41)
|
|
|
|
|
.Case("+ssse3", SSSE3)
|
|
|
|
|
.Case("+sse3", SSE3)
|
|
|
|
|
.Case("+sse2", SSE2)
|
|
|
|
|
.Case("+sse", SSE1)
|
|
|
|
|
.Default(NoSSE);
|
|
|
|
|
SSELevel = std::max(SSELevel, Level);
|
|
|
|
|
|
|
|
|
|
MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
|
|
|
|
|
.Case("+3dnowa", AMD3DNowAthlon)
|
|
|
|
|
.Case("+3dnow", AMD3DNow)
|
|
|
|
|
.Case("+mmx", MMX)
|
|
|
|
|
.Default(NoMMX3DNow);
|
|
|
|
|
MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
|
|
|
|
|
|
|
|
|
|
XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
|
|
|
|
|
.Case("+xop", XOP)
|
|
|
|
|
.Case("+fma4", FMA4)
|
|
|
|
|
.Case("+sse4a", SSE4A)
|
|
|
|
|
.Default(NoXOP);
|
|
|
|
|
XOPLevel = std::max(XOPLevel, XLevel);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// LLVM doesn't have a separate switch for fpmath, so only accept it if it
|
|
|
|
|
// matches the selected sse level.
|
|
|
|
|
if ((FPMath == FP_SSE && SSELevel < SSE1) ||
|
|
|
|
|
(FPMath == FP_387 && SSELevel >= SSE1)) {
|
|
|
|
|
Diags.Report(diag::err_target_unsupported_fpmath)
|
|
|
|
|
<< (FPMath == FP_SSE ? "sse" : "387");
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
SimdDefaultAlign =
|
|
|
|
|
hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
|
|
|
|
|
/// definitions for this particular subtarget.
|
|
|
|
|
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
|
|
|
|
|
MacroBuilder &Builder) const {
|
|
|
|
|
// Target identification.
|
|
|
|
|
if (getTriple().getArch() == llvm::Triple::x86_64) {
|
|
|
|
|
Builder.defineMacro("__amd64__");
|
|
|
|
|
Builder.defineMacro("__amd64");
|
|
|
|
|
Builder.defineMacro("__x86_64");
|
|
|
|
|
Builder.defineMacro("__x86_64__");
|
|
|
|
|
if (getTriple().getArchName() == "x86_64h") {
|
|
|
|
|
Builder.defineMacro("__x86_64h");
|
|
|
|
|
Builder.defineMacro("__x86_64h__");
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
DefineStd(Builder, "i386", Opts);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Subtarget options.
|
|
|
|
|
// FIXME: We are hard-coding the tune parameters based on the CPU, but they
|
|
|
|
|
// truly should be based on -mtune options.
|
|
|
|
|
switch (CPU) {
|
|
|
|
|
case CK_Generic:
|
|
|
|
|
break;
|
|
|
|
|
case CK_i386:
|
|
|
|
|
// The rest are coming from the i386 define above.
|
|
|
|
|
Builder.defineMacro("__tune_i386__");
|
|
|
|
|
break;
|
|
|
|
|
case CK_i486:
|
|
|
|
|
case CK_WinChipC6:
|
|
|
|
|
case CK_WinChip2:
|
|
|
|
|
case CK_C3:
|
|
|
|
|
defineCPUMacros(Builder, "i486");
|
|
|
|
|
break;
|
|
|
|
|
case CK_PentiumMMX:
|
|
|
|
|
Builder.defineMacro("__pentium_mmx__");
|
|
|
|
|
Builder.defineMacro("__tune_pentium_mmx__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_i586:
|
|
|
|
|
case CK_Pentium:
|
|
|
|
|
defineCPUMacros(Builder, "i586");
|
|
|
|
|
defineCPUMacros(Builder, "pentium");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Pentium3:
|
|
|
|
|
case CK_PentiumM:
|
|
|
|
|
Builder.defineMacro("__tune_pentium3__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_Pentium2:
|
|
|
|
|
case CK_C3_2:
|
|
|
|
|
Builder.defineMacro("__tune_pentium2__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_PentiumPro:
|
2017-10-27 07:06:19 +08:00
|
|
|
defineCPUMacros(Builder, "i686");
|
|
|
|
|
defineCPUMacros(Builder, "pentiumpro");
|
2017-07-22 06:37:03 +08:00
|
|
|
break;
|
|
|
|
|
case CK_Pentium4:
|
|
|
|
|
defineCPUMacros(Builder, "pentium4");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Yonah:
|
|
|
|
|
case CK_Prescott:
|
|
|
|
|
case CK_Nocona:
|
|
|
|
|
defineCPUMacros(Builder, "nocona");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Core2:
|
|
|
|
|
case CK_Penryn:
|
|
|
|
|
defineCPUMacros(Builder, "core2");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Bonnell:
|
|
|
|
|
defineCPUMacros(Builder, "atom");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Silvermont:
|
|
|
|
|
defineCPUMacros(Builder, "slm");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Goldmont:
|
|
|
|
|
defineCPUMacros(Builder, "goldmont");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Nehalem:
|
|
|
|
|
case CK_Westmere:
|
|
|
|
|
case CK_SandyBridge:
|
|
|
|
|
case CK_IvyBridge:
|
|
|
|
|
case CK_Haswell:
|
|
|
|
|
case CK_Broadwell:
|
|
|
|
|
case CK_SkylakeClient:
|
2017-11-19 10:55:14 +08:00
|
|
|
case CK_SkylakeServer:
|
|
|
|
|
case CK_Cannonlake:
|
2017-11-19 10:55:15 +08:00
|
|
|
case CK_Icelake:
|
2017-07-22 06:37:03 +08:00
|
|
|
// FIXME: Historically, we defined this legacy name, it would be nice to
|
|
|
|
|
// remove it at some point. We've never exposed fine-grained names for
|
|
|
|
|
// recent primary x86 CPUs, and we should keep it that way.
|
|
|
|
|
defineCPUMacros(Builder, "corei7");
|
|
|
|
|
break;
|
|
|
|
|
case CK_KNL:
|
|
|
|
|
defineCPUMacros(Builder, "knl");
|
|
|
|
|
break;
|
2017-10-14 02:14:24 +08:00
|
|
|
case CK_KNM:
|
|
|
|
|
break;
|
2017-07-22 06:37:03 +08:00
|
|
|
case CK_Lakemont:
|
2017-11-01 10:18:49 +08:00
|
|
|
defineCPUMacros(Builder, "i586", /*Tuning*/false);
|
|
|
|
|
defineCPUMacros(Builder, "pentium", /*Tuning*/false);
|
2017-07-22 06:37:03 +08:00
|
|
|
Builder.defineMacro("__tune_lakemont__");
|
|
|
|
|
break;
|
|
|
|
|
case CK_K6_2:
|
|
|
|
|
Builder.defineMacro("__k6_2__");
|
|
|
|
|
Builder.defineMacro("__tune_k6_2__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_K6_3:
|
|
|
|
|
if (CPU != CK_K6_2) { // In case of fallthrough
|
|
|
|
|
// FIXME: GCC may be enabling these in cases where some other k6
|
|
|
|
|
// architecture is specified but -m3dnow is explicitly provided. The
|
|
|
|
|
// exact semantics need to be determined and emulated here.
|
|
|
|
|
Builder.defineMacro("__k6_3__");
|
|
|
|
|
Builder.defineMacro("__tune_k6_3__");
|
|
|
|
|
}
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case CK_K6:
|
|
|
|
|
defineCPUMacros(Builder, "k6");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Athlon:
|
|
|
|
|
case CK_AthlonXP:
|
|
|
|
|
defineCPUMacros(Builder, "athlon");
|
|
|
|
|
if (SSELevel != NoSSE) {
|
|
|
|
|
Builder.defineMacro("__athlon_sse__");
|
|
|
|
|
Builder.defineMacro("__tune_athlon_sse__");
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case CK_K8:
|
|
|
|
|
case CK_K8SSE3:
|
|
|
|
|
case CK_x86_64:
|
|
|
|
|
defineCPUMacros(Builder, "k8");
|
|
|
|
|
break;
|
|
|
|
|
case CK_AMDFAM10:
|
|
|
|
|
defineCPUMacros(Builder, "amdfam10");
|
|
|
|
|
break;
|
|
|
|
|
case CK_BTVER1:
|
|
|
|
|
defineCPUMacros(Builder, "btver1");
|
|
|
|
|
break;
|
|
|
|
|
case CK_BTVER2:
|
|
|
|
|
defineCPUMacros(Builder, "btver2");
|
|
|
|
|
break;
|
|
|
|
|
case CK_BDVER1:
|
|
|
|
|
defineCPUMacros(Builder, "bdver1");
|
|
|
|
|
break;
|
|
|
|
|
case CK_BDVER2:
|
|
|
|
|
defineCPUMacros(Builder, "bdver2");
|
|
|
|
|
break;
|
|
|
|
|
case CK_BDVER3:
|
|
|
|
|
defineCPUMacros(Builder, "bdver3");
|
|
|
|
|
break;
|
|
|
|
|
case CK_BDVER4:
|
|
|
|
|
defineCPUMacros(Builder, "bdver4");
|
|
|
|
|
break;
|
|
|
|
|
case CK_ZNVER1:
|
|
|
|
|
defineCPUMacros(Builder, "znver1");
|
|
|
|
|
break;
|
|
|
|
|
case CK_Geode:
|
|
|
|
|
defineCPUMacros(Builder, "geode");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Target properties.
|
|
|
|
|
Builder.defineMacro("__REGISTER_PREFIX__", "");
|
|
|
|
|
|
|
|
|
|
// Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
|
|
|
|
|
// functions in glibc header files that use FP Stack inline asm which the
|
|
|
|
|
// backend can't deal with (PR879).
|
|
|
|
|
Builder.defineMacro("__NO_MATH_INLINES");
|
|
|
|
|
|
|
|
|
|
if (HasAES)
|
|
|
|
|
Builder.defineMacro("__AES__");
|
|
|
|
|
|
2017-12-27 16:16:54 +08:00
|
|
|
if (HasVAES)
|
|
|
|
|
Builder.defineMacro("__VAES__");
|
|
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasPCLMUL)
|
|
|
|
|
Builder.defineMacro("__PCLMUL__");
|
|
|
|
|
|
2017-12-27 17:00:31 +08:00
|
|
|
if (HasVPCLMULQDQ)
|
|
|
|
|
Builder.defineMacro("__VPCLMULQDQ__");
|
|
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasLZCNT)
|
|
|
|
|
Builder.defineMacro("__LZCNT__");
|
|
|
|
|
|
|
|
|
|
if (HasRDRND)
|
|
|
|
|
Builder.defineMacro("__RDRND__");
|
|
|
|
|
|
|
|
|
|
if (HasFSGSBASE)
|
|
|
|
|
Builder.defineMacro("__FSGSBASE__");
|
|
|
|
|
|
|
|
|
|
if (HasBMI)
|
|
|
|
|
Builder.defineMacro("__BMI__");
|
|
|
|
|
|
|
|
|
|
if (HasBMI2)
|
|
|
|
|
Builder.defineMacro("__BMI2__");
|
|
|
|
|
|
|
|
|
|
if (HasPOPCNT)
|
|
|
|
|
Builder.defineMacro("__POPCNT__");
|
|
|
|
|
|
|
|
|
|
if (HasRTM)
|
|
|
|
|
Builder.defineMacro("__RTM__");
|
|
|
|
|
|
|
|
|
|
if (HasPRFCHW)
|
|
|
|
|
Builder.defineMacro("__PRFCHW__");
|
|
|
|
|
|
|
|
|
|
if (HasRDSEED)
|
|
|
|
|
Builder.defineMacro("__RDSEED__");
|
|
|
|
|
|
|
|
|
|
if (HasADX)
|
|
|
|
|
Builder.defineMacro("__ADX__");
|
|
|
|
|
|
|
|
|
|
if (HasTBM)
|
|
|
|
|
Builder.defineMacro("__TBM__");
|
|
|
|
|
|
|
|
|
|
if (HasLWP)
|
|
|
|
|
Builder.defineMacro("__LWP__");
|
|
|
|
|
|
|
|
|
|
if (HasMWAITX)
|
|
|
|
|
Builder.defineMacro("__MWAITX__");
|
|
|
|
|
|
|
|
|
|
switch (XOPLevel) {
|
|
|
|
|
case XOP:
|
|
|
|
|
Builder.defineMacro("__XOP__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case FMA4:
|
|
|
|
|
Builder.defineMacro("__FMA4__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE4A:
|
|
|
|
|
Builder.defineMacro("__SSE4A__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case NoXOP:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (HasFMA)
|
|
|
|
|
Builder.defineMacro("__FMA__");
|
|
|
|
|
|
|
|
|
|
if (HasF16C)
|
|
|
|
|
Builder.defineMacro("__F16C__");
|
|
|
|
|
|
2017-12-27 16:37:47 +08:00
|
|
|
if (HasGFNI)
|
|
|
|
|
Builder.defineMacro("__GFNI__");
|
|
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasAVX512CD)
|
|
|
|
|
Builder.defineMacro("__AVX512CD__");
|
|
|
|
|
if (HasAVX512VPOPCNTDQ)
|
|
|
|
|
Builder.defineMacro("__AVX512VPOPCNTDQ__");
|
2017-12-27 18:37:51 +08:00
|
|
|
if (HasAVX512VNNI)
|
|
|
|
|
Builder.defineMacro("__AVX512VNNI__");
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasAVX512ER)
|
|
|
|
|
Builder.defineMacro("__AVX512ER__");
|
|
|
|
|
if (HasAVX512PF)
|
|
|
|
|
Builder.defineMacro("__AVX512PF__");
|
|
|
|
|
if (HasAVX512DQ)
|
|
|
|
|
Builder.defineMacro("__AVX512DQ__");
|
2017-12-27 18:01:00 +08:00
|
|
|
if (HasAVX512BITALG)
|
|
|
|
|
Builder.defineMacro("__AVX512BITALG__");
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasAVX512BW)
|
|
|
|
|
Builder.defineMacro("__AVX512BW__");
|
|
|
|
|
if (HasAVX512VL)
|
|
|
|
|
Builder.defineMacro("__AVX512VL__");
|
|
|
|
|
if (HasAVX512VBMI)
|
|
|
|
|
Builder.defineMacro("__AVX512VBMI__");
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
if (HasAVX512VBMI2)
|
|
|
|
|
Builder.defineMacro("__AVX512VBMI2__");
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasAVX512IFMA)
|
|
|
|
|
Builder.defineMacro("__AVX512IFMA__");
|
|
|
|
|
|
|
|
|
|
if (HasSHA)
|
|
|
|
|
Builder.defineMacro("__SHA__");
|
|
|
|
|
|
|
|
|
|
if (HasFXSR)
|
|
|
|
|
Builder.defineMacro("__FXSR__");
|
|
|
|
|
if (HasXSAVE)
|
|
|
|
|
Builder.defineMacro("__XSAVE__");
|
|
|
|
|
if (HasXSAVEOPT)
|
|
|
|
|
Builder.defineMacro("__XSAVEOPT__");
|
|
|
|
|
if (HasXSAVEC)
|
|
|
|
|
Builder.defineMacro("__XSAVEC__");
|
|
|
|
|
if (HasXSAVES)
|
|
|
|
|
Builder.defineMacro("__XSAVES__");
|
|
|
|
|
if (HasPKU)
|
|
|
|
|
Builder.defineMacro("__PKU__");
|
|
|
|
|
if (HasCLFLUSHOPT)
|
|
|
|
|
Builder.defineMacro("__CLFLUSHOPT__");
|
|
|
|
|
if (HasCLWB)
|
|
|
|
|
Builder.defineMacro("__CLWB__");
|
|
|
|
|
if (HasMPX)
|
|
|
|
|
Builder.defineMacro("__MPX__");
|
2017-11-26 20:34:54 +08:00
|
|
|
if (HasSHSTK)
|
|
|
|
|
Builder.defineMacro("__SHSTK__");
|
2018-01-27 02:31:14 +08:00
|
|
|
if (HasIBT)
|
|
|
|
|
Builder.defineMacro("__IBT__");
|
2017-07-22 06:37:03 +08:00
|
|
|
if (HasSGX)
|
|
|
|
|
Builder.defineMacro("__SGX__");
|
|
|
|
|
if (HasPREFETCHWT1)
|
|
|
|
|
Builder.defineMacro("__PREFETCHWT1__");
|
|
|
|
|
if (HasCLZERO)
|
|
|
|
|
Builder.defineMacro("__CLZERO__");
|
2018-01-21 02:36:52 +08:00
|
|
|
if (HasRDPID)
|
|
|
|
|
Builder.defineMacro("__RDPID__");
|
2017-07-22 06:37:03 +08:00
|
|
|
|
|
|
|
|
// Each case falls through to the previous one here.
|
|
|
|
|
switch (SSELevel) {
|
|
|
|
|
case AVX512F:
|
|
|
|
|
Builder.defineMacro("__AVX512F__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX2:
|
|
|
|
|
Builder.defineMacro("__AVX2__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AVX:
|
|
|
|
|
Builder.defineMacro("__AVX__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE42:
|
|
|
|
|
Builder.defineMacro("__SSE4_2__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE41:
|
|
|
|
|
Builder.defineMacro("__SSE4_1__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSSE3:
|
|
|
|
|
Builder.defineMacro("__SSSE3__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE3:
|
|
|
|
|
Builder.defineMacro("__SSE3__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE2:
|
|
|
|
|
Builder.defineMacro("__SSE2__");
|
|
|
|
|
Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case SSE1:
|
|
|
|
|
Builder.defineMacro("__SSE__");
|
|
|
|
|
Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case NoSSE:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
|
|
|
|
|
switch (SSELevel) {
|
|
|
|
|
case AVX512F:
|
|
|
|
|
case AVX2:
|
|
|
|
|
case AVX:
|
|
|
|
|
case SSE42:
|
|
|
|
|
case SSE41:
|
|
|
|
|
case SSSE3:
|
|
|
|
|
case SSE3:
|
|
|
|
|
case SSE2:
|
|
|
|
|
Builder.defineMacro("_M_IX86_FP", Twine(2));
|
|
|
|
|
break;
|
|
|
|
|
case SSE1:
|
|
|
|
|
Builder.defineMacro("_M_IX86_FP", Twine(1));
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
Builder.defineMacro("_M_IX86_FP", Twine(0));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Each case falls through to the previous one here.
|
|
|
|
|
switch (MMX3DNowLevel) {
|
|
|
|
|
case AMD3DNowAthlon:
|
|
|
|
|
Builder.defineMacro("__3dNOW_A__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case AMD3DNow:
|
|
|
|
|
Builder.defineMacro("__3dNOW__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case MMX:
|
|
|
|
|
Builder.defineMacro("__MMX__");
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
case NoMMX3DNow:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (CPU >= CK_i486) {
|
|
|
|
|
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
|
|
|
|
|
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
|
|
|
|
|
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
|
|
|
|
|
}
|
|
|
|
|
if (CPU >= CK_i586)
|
|
|
|
|
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
|
2018-01-21 02:36:06 +08:00
|
|
|
if (HasCX16)
|
|
|
|
|
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
|
2017-07-22 06:37:03 +08:00
|
|
|
|
|
|
|
|
if (HasFloat128)
|
|
|
|
|
Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
|
|
|
|
|
return llvm::StringSwitch<bool>(Name)
|
2017-11-07 04:33:13 +08:00
|
|
|
.Case("3dnow", true)
|
|
|
|
|
.Case("3dnowa", true)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("adx", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("aes", true)
|
|
|
|
|
.Case("avx", true)
|
|
|
|
|
.Case("avx2", true)
|
|
|
|
|
.Case("avx512f", true)
|
|
|
|
|
.Case("avx512cd", true)
|
|
|
|
|
.Case("avx512vpopcntdq", true)
|
2017-12-27 18:37:51 +08:00
|
|
|
.Case("avx512vnni", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("avx512er", true)
|
|
|
|
|
.Case("avx512pf", true)
|
|
|
|
|
.Case("avx512dq", true)
|
2017-12-27 18:01:00 +08:00
|
|
|
.Case("avx512bitalg", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("avx512bw", true)
|
|
|
|
|
.Case("avx512vl", true)
|
|
|
|
|
.Case("avx512vbmi", true)
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
.Case("avx512vbmi2", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("avx512ifma", true)
|
|
|
|
|
.Case("bmi", true)
|
|
|
|
|
.Case("bmi2", true)
|
|
|
|
|
.Case("clflushopt", true)
|
|
|
|
|
.Case("clwb", true)
|
|
|
|
|
.Case("clzero", true)
|
|
|
|
|
.Case("cx16", true)
|
|
|
|
|
.Case("f16c", true)
|
|
|
|
|
.Case("fma", true)
|
|
|
|
|
.Case("fma4", true)
|
|
|
|
|
.Case("fsgsbase", true)
|
|
|
|
|
.Case("fxsr", true)
|
2017-12-27 16:37:47 +08:00
|
|
|
.Case("gfni", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("lwp", true)
|
|
|
|
|
.Case("lzcnt", true)
|
|
|
|
|
.Case("mmx", true)
|
|
|
|
|
.Case("movbe", true)
|
|
|
|
|
.Case("mpx", true)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("mwaitx", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("pclmul", true)
|
|
|
|
|
.Case("pku", true)
|
|
|
|
|
.Case("popcnt", true)
|
|
|
|
|
.Case("prefetchwt1", true)
|
|
|
|
|
.Case("prfchw", true)
|
2018-01-21 02:36:52 +08:00
|
|
|
.Case("rdpid", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("rdrnd", true)
|
|
|
|
|
.Case("rdseed", true)
|
|
|
|
|
.Case("rtm", true)
|
|
|
|
|
.Case("sgx", true)
|
|
|
|
|
.Case("sha", true)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("shstk", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("sse", true)
|
|
|
|
|
.Case("sse2", true)
|
|
|
|
|
.Case("sse3", true)
|
|
|
|
|
.Case("ssse3", true)
|
2017-10-27 08:18:16 +08:00
|
|
|
.Case("sse4", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("sse4.1", true)
|
|
|
|
|
.Case("sse4.2", true)
|
|
|
|
|
.Case("sse4a", true)
|
|
|
|
|
.Case("tbm", true)
|
2017-12-27 16:16:54 +08:00
|
|
|
.Case("vaes", true)
|
2017-12-27 17:00:31 +08:00
|
|
|
.Case("vpclmulqdq", true)
|
2017-10-28 02:32:23 +08:00
|
|
|
.Case("x87", true)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("xop", true)
|
|
|
|
|
.Case("xsave", true)
|
|
|
|
|
.Case("xsavec", true)
|
|
|
|
|
.Case("xsaves", true)
|
|
|
|
|
.Case("xsaveopt", true)
|
|
|
|
|
.Default(false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool X86TargetInfo::hasFeature(StringRef Feature) const {
|
|
|
|
|
return llvm::StringSwitch<bool>(Feature)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("adx", HasADX)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("aes", HasAES)
|
|
|
|
|
.Case("avx", SSELevel >= AVX)
|
|
|
|
|
.Case("avx2", SSELevel >= AVX2)
|
|
|
|
|
.Case("avx512f", SSELevel >= AVX512F)
|
|
|
|
|
.Case("avx512cd", HasAVX512CD)
|
|
|
|
|
.Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
|
2017-12-27 18:37:51 +08:00
|
|
|
.Case("avx512vnni", HasAVX512VNNI)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("avx512er", HasAVX512ER)
|
|
|
|
|
.Case("avx512pf", HasAVX512PF)
|
|
|
|
|
.Case("avx512dq", HasAVX512DQ)
|
2017-12-27 18:01:00 +08:00
|
|
|
.Case("avx512bitalg", HasAVX512BITALG)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("avx512bw", HasAVX512BW)
|
|
|
|
|
.Case("avx512vl", HasAVX512VL)
|
|
|
|
|
.Case("avx512vbmi", HasAVX512VBMI)
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
.Case("avx512vbmi2", HasAVX512VBMI2)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("avx512ifma", HasAVX512IFMA)
|
|
|
|
|
.Case("bmi", HasBMI)
|
|
|
|
|
.Case("bmi2", HasBMI2)
|
|
|
|
|
.Case("clflushopt", HasCLFLUSHOPT)
|
|
|
|
|
.Case("clwb", HasCLWB)
|
|
|
|
|
.Case("clzero", HasCLZERO)
|
|
|
|
|
.Case("cx16", HasCX16)
|
|
|
|
|
.Case("f16c", HasF16C)
|
|
|
|
|
.Case("fma", HasFMA)
|
|
|
|
|
.Case("fma4", XOPLevel >= FMA4)
|
|
|
|
|
.Case("fsgsbase", HasFSGSBASE)
|
|
|
|
|
.Case("fxsr", HasFXSR)
|
2017-12-27 16:37:47 +08:00
|
|
|
.Case("gfni", HasGFNI)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("ibt", HasIBT)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("lwp", HasLWP)
|
|
|
|
|
.Case("lzcnt", HasLZCNT)
|
|
|
|
|
.Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
|
|
|
|
|
.Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
|
|
|
|
|
.Case("mmx", MMX3DNowLevel >= MMX)
|
|
|
|
|
.Case("movbe", HasMOVBE)
|
|
|
|
|
.Case("mpx", HasMPX)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("mwaitx", HasMWAITX)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("pclmul", HasPCLMUL)
|
|
|
|
|
.Case("pku", HasPKU)
|
|
|
|
|
.Case("popcnt", HasPOPCNT)
|
|
|
|
|
.Case("prefetchwt1", HasPREFETCHWT1)
|
|
|
|
|
.Case("prfchw", HasPRFCHW)
|
2018-01-21 02:36:52 +08:00
|
|
|
.Case("rdpid", HasRDPID)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("rdrnd", HasRDRND)
|
|
|
|
|
.Case("rdseed", HasRDSEED)
|
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
|
|
|
.Case("retpoline", HasRetpoline)
|
|
|
|
|
.Case("retpoline-external-thunk", HasRetpolineExternalThunk)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("rtm", HasRTM)
|
|
|
|
|
.Case("sgx", HasSGX)
|
|
|
|
|
.Case("sha", HasSHA)
|
2017-12-22 07:27:36 +08:00
|
|
|
.Case("shstk", HasSHSTK)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("sse", SSELevel >= SSE1)
|
|
|
|
|
.Case("sse2", SSELevel >= SSE2)
|
|
|
|
|
.Case("sse3", SSELevel >= SSE3)
|
|
|
|
|
.Case("ssse3", SSELevel >= SSSE3)
|
|
|
|
|
.Case("sse4.1", SSELevel >= SSE41)
|
|
|
|
|
.Case("sse4.2", SSELevel >= SSE42)
|
|
|
|
|
.Case("sse4a", XOPLevel >= SSE4A)
|
|
|
|
|
.Case("tbm", HasTBM)
|
2017-12-27 16:16:54 +08:00
|
|
|
.Case("vaes", HasVAES)
|
2017-12-27 17:00:31 +08:00
|
|
|
.Case("vpclmulqdq", HasVPCLMULQDQ)
|
2017-07-22 06:37:03 +08:00
|
|
|
.Case("x86", true)
|
|
|
|
|
.Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
|
|
|
|
|
.Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
|
|
|
|
|
.Case("xop", XOPLevel >= XOP)
|
|
|
|
|
.Case("xsave", HasXSAVE)
|
|
|
|
|
.Case("xsavec", HasXSAVEC)
|
|
|
|
|
.Case("xsaves", HasXSAVES)
|
|
|
|
|
.Case("xsaveopt", HasXSAVEOPT)
|
|
|
|
|
.Default(false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// We can't use a generic validation scheme for the features accepted here
|
|
|
|
|
// versus subtarget features accepted in the target attribute because the
|
|
|
|
|
// bitfield structure that's initialized in the runtime only supports the
|
|
|
|
|
// below currently rather than the full range of subtarget features. (See
|
|
|
|
|
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
|
|
|
|
|
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
|
|
|
|
|
return llvm::StringSwitch<bool>(FeatureStr)
|
2017-11-22 08:54:01 +08:00
|
|
|
#define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
|
|
|
|
|
#include "llvm/Support/X86TargetParser.def"
|
2017-07-22 06:37:03 +08:00
|
|
|
.Default(false);
|
|
|
|
|
}
|
|
|
|
|
|
Implement Attribute Target MultiVersioning
GCC's attribute 'target', in addition to being an optimization hint,
also allows function multiversioning. We currently have the former
implemented, this is the latter's implementation.
This works by enabling functions with the same name/signature to coexist,
so that they can all be emitted. Multiversion state is stored in the
FunctionDecl itself, and SemaDecl manages the definitions.
Note that it ends up having to permit redefinition of functions so
that they can all be emitted. Additionally, all versions of the function
must be emitted, so this also manages that.
Note that this includes some additional rules that GCC does not, since
defining something as a MultiVersion function after a usage has been made illegal.
The only 'history rewriting' that happens is if a function is emitted before
it has been converted to a multiversion'ed function, at which point its name
needs to be changed.
Function templates and virtual functions are NOT yet supported (not supported
in GCC either).
Additionally, constructors/destructors are disallowed, but the former is
planned.
llvm-svn: 322028
2018-01-09 05:34:17 +08:00
|
|
|
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
|
|
|
|
|
return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
|
|
|
|
|
#define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
|
|
|
|
|
#include "llvm/Support/X86TargetParser.def"
|
|
|
|
|
;
|
|
|
|
|
// Note, this function should only be used after ensuring the value is
|
|
|
|
|
// correct, so it asserts if the value is out of range.
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
|
|
|
|
|
enum class FeatPriority {
|
|
|
|
|
#define FEATURE(FEAT) FEAT,
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
|
|
|
|
};
|
|
|
|
|
switch (Feat) {
|
|
|
|
|
#define FEATURE(FEAT) \
|
|
|
|
|
case llvm::X86::FEAT: \
|
|
|
|
|
return static_cast<unsigned>(FeatPriority::FEAT);
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
|
|
|
|
default:
|
|
|
|
|
llvm_unreachable("No Feature Priority for non-CPUSupports Features");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
|
|
|
|
|
// Valid CPUs have a 'key feature' that compares just better than its key
|
|
|
|
|
// feature.
|
|
|
|
|
CPUKind Kind = getCPUKind(Name);
|
|
|
|
|
if (Kind != CK_Generic) {
|
|
|
|
|
switch (Kind) {
|
|
|
|
|
default:
|
|
|
|
|
llvm_unreachable(
|
|
|
|
|
"CPU Type without a key feature used in 'target' attribute");
|
|
|
|
|
#define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
|
|
|
|
|
case CK_##ENUM: \
|
|
|
|
|
return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Now we know we have a feature, so get its priority and shift it a few so
|
|
|
|
|
// that we have sufficient room for the CPUs (above).
|
|
|
|
|
return getFeaturePriority(getFeature(Name)) << 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const {
|
|
|
|
|
switch (Kind) {
|
|
|
|
|
case CK_Generic:
|
|
|
|
|
return "";
|
|
|
|
|
#define PROC(ENUM, STRING, IS64BIT) \
|
|
|
|
|
case CK_##ENUM: \
|
|
|
|
|
return STRING;
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
|
|
|
|
}
|
|
|
|
|
llvm_unreachable("Invalid CPUKind");
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-11 04:28:30 +08:00
|
|
|
// We can't use a generic validation scheme for the cpus accepted here
|
|
|
|
|
// versus subtarget cpus accepted in the target attribute because the
|
|
|
|
|
// variables intitialized by the runtime only support the below currently
|
|
|
|
|
// rather than the full range of cpus.
|
|
|
|
|
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
|
|
|
|
|
return llvm::StringSwitch<bool>(FeatureStr)
|
2017-11-15 08:11:24 +08:00
|
|
|
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
|
|
|
|
|
#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
|
|
|
|
|
.Cases(STR, ALIAS, true)
|
|
|
|
|
#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
|
|
|
|
|
#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
|
|
|
|
|
#include "llvm/Support/X86TargetParser.def"
|
2017-08-11 04:28:30 +08:00
|
|
|
.Default(false);
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
bool X86TargetInfo::validateAsmConstraint(
|
|
|
|
|
const char *&Name, TargetInfo::ConstraintInfo &Info) const {
|
|
|
|
|
switch (*Name) {
|
|
|
|
|
default:
|
|
|
|
|
return false;
|
|
|
|
|
// Constant constraints.
|
|
|
|
|
case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
|
|
|
|
|
// instructions.
|
|
|
|
|
case 'Z': // 32-bit unsigned integer constant for use with zero-extending
|
|
|
|
|
// x86_64 instructions.
|
|
|
|
|
case 's':
|
|
|
|
|
Info.setRequiresImmediate();
|
|
|
|
|
return true;
|
|
|
|
|
case 'I':
|
|
|
|
|
Info.setRequiresImmediate(0, 31);
|
|
|
|
|
return true;
|
|
|
|
|
case 'J':
|
|
|
|
|
Info.setRequiresImmediate(0, 63);
|
|
|
|
|
return true;
|
|
|
|
|
case 'K':
|
|
|
|
|
Info.setRequiresImmediate(-128, 127);
|
|
|
|
|
return true;
|
|
|
|
|
case 'L':
|
|
|
|
|
Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
|
|
|
|
|
return true;
|
|
|
|
|
case 'M':
|
|
|
|
|
Info.setRequiresImmediate(0, 3);
|
|
|
|
|
return true;
|
|
|
|
|
case 'N':
|
|
|
|
|
Info.setRequiresImmediate(0, 255);
|
|
|
|
|
return true;
|
|
|
|
|
case 'O':
|
|
|
|
|
Info.setRequiresImmediate(0, 127);
|
|
|
|
|
return true;
|
|
|
|
|
// Register constraints.
|
|
|
|
|
case 'Y': // 'Y' is the first character for several 2-character constraints.
|
|
|
|
|
// Shift the pointer to the second character of the constraint.
|
|
|
|
|
Name++;
|
|
|
|
|
switch (*Name) {
|
|
|
|
|
default:
|
|
|
|
|
return false;
|
2017-08-24 17:07:34 +08:00
|
|
|
case 'z':
|
2017-07-22 06:37:03 +08:00
|
|
|
case '0': // First SSE register.
|
2017-08-24 17:07:34 +08:00
|
|
|
case '2':
|
2017-07-22 06:37:03 +08:00
|
|
|
case 't': // Any SSE register, when SSE2 is enabled.
|
|
|
|
|
case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
|
|
|
|
|
case 'm': // Any MMX register, when inter-unit moves enabled.
|
|
|
|
|
case 'k': // AVX512 arch mask registers: k1-k7.
|
|
|
|
|
Info.setAllowsRegister();
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
case 'f': // Any x87 floating point stack register.
|
|
|
|
|
// Constraint 'f' cannot be used for output operands.
|
|
|
|
|
if (Info.ConstraintStr[0] == '=')
|
|
|
|
|
return false;
|
|
|
|
|
Info.setAllowsRegister();
|
|
|
|
|
return true;
|
|
|
|
|
case 'a': // eax.
|
|
|
|
|
case 'b': // ebx.
|
|
|
|
|
case 'c': // ecx.
|
|
|
|
|
case 'd': // edx.
|
|
|
|
|
case 'S': // esi.
|
|
|
|
|
case 'D': // edi.
|
|
|
|
|
case 'A': // edx:eax.
|
|
|
|
|
case 't': // Top of floating point stack.
|
|
|
|
|
case 'u': // Second from top of floating point stack.
|
|
|
|
|
case 'q': // Any register accessible as [r]l: a, b, c, and d.
|
|
|
|
|
case 'y': // Any MMX register.
|
|
|
|
|
case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
|
|
|
|
|
case 'x': // Any SSE register.
|
|
|
|
|
case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
|
|
|
|
|
// for intermideate k reg operations).
|
|
|
|
|
case 'Q': // Any register accessible as [r]h: a, b, c, and d.
|
|
|
|
|
case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
|
|
|
|
|
case 'l': // "Index" registers: any general register that can be used as an
|
|
|
|
|
// index in a base+index memory access.
|
|
|
|
|
Info.setAllowsRegister();
|
|
|
|
|
return true;
|
|
|
|
|
// Floating point constant constraints.
|
|
|
|
|
case 'C': // SSE floating point constant.
|
|
|
|
|
case 'G': // x87 floating point constant.
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool X86TargetInfo::validateOutputSize(StringRef Constraint,
|
|
|
|
|
unsigned Size) const {
|
|
|
|
|
// Strip off constraint modifiers.
|
|
|
|
|
while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
|
|
|
|
|
Constraint = Constraint.substr(1);
|
|
|
|
|
|
|
|
|
|
return validateOperandSize(Constraint, Size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool X86TargetInfo::validateInputSize(StringRef Constraint,
|
|
|
|
|
unsigned Size) const {
|
|
|
|
|
return validateOperandSize(Constraint, Size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool X86TargetInfo::validateOperandSize(StringRef Constraint,
|
|
|
|
|
unsigned Size) const {
|
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
case 'k':
|
|
|
|
|
// Registers k0-k7 (AVX512) size limit is 64 bit.
|
|
|
|
|
case 'y':
|
|
|
|
|
return Size <= 64;
|
|
|
|
|
case 'f':
|
|
|
|
|
case 't':
|
|
|
|
|
case 'u':
|
|
|
|
|
return Size <= 128;
|
|
|
|
|
case 'Y':
|
|
|
|
|
// 'Y' is the first character for several 2-character constraints.
|
|
|
|
|
switch (Constraint[1]) {
|
|
|
|
|
default:
|
2017-08-24 17:07:34 +08:00
|
|
|
return false;
|
2017-07-22 06:37:03 +08:00
|
|
|
case 'm':
|
|
|
|
|
// 'Ym' is synonymous with 'y'.
|
|
|
|
|
case 'k':
|
|
|
|
|
return Size <= 64;
|
2017-08-24 17:07:34 +08:00
|
|
|
case 'z':
|
|
|
|
|
case '0':
|
|
|
|
|
// XMM0
|
|
|
|
|
if (SSELevel >= SSE1)
|
|
|
|
|
return Size <= 128U;
|
|
|
|
|
return false;
|
2017-07-22 06:37:03 +08:00
|
|
|
case 'i':
|
|
|
|
|
case 't':
|
2017-08-24 17:07:34 +08:00
|
|
|
case '2':
|
|
|
|
|
// 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
|
|
|
|
|
if (SSELevel < SSE2)
|
|
|
|
|
return false;
|
|
|
|
|
break;
|
2017-07-22 06:37:03 +08:00
|
|
|
}
|
2017-08-24 17:07:34 +08:00
|
|
|
case 'v':
|
|
|
|
|
case 'x':
|
|
|
|
|
if (SSELevel >= AVX512F)
|
|
|
|
|
// 512-bit zmm registers can be used if target supports AVX512F.
|
|
|
|
|
return Size <= 512U;
|
|
|
|
|
else if (SSELevel >= AVX)
|
|
|
|
|
// 256-bit ymm registers can be used if target supports AVX.
|
|
|
|
|
return Size <= 256U;
|
|
|
|
|
return Size <= 128U;
|
|
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
|
|
|
|
|
switch (*Constraint) {
|
|
|
|
|
case 'a':
|
|
|
|
|
return std::string("{ax}");
|
|
|
|
|
case 'b':
|
|
|
|
|
return std::string("{bx}");
|
|
|
|
|
case 'c':
|
|
|
|
|
return std::string("{cx}");
|
|
|
|
|
case 'd':
|
|
|
|
|
return std::string("{dx}");
|
|
|
|
|
case 'S':
|
|
|
|
|
return std::string("{si}");
|
|
|
|
|
case 'D':
|
|
|
|
|
return std::string("{di}");
|
|
|
|
|
case 'p': // address
|
|
|
|
|
return std::string("im");
|
|
|
|
|
case 't': // top of floating point stack.
|
|
|
|
|
return std::string("{st}");
|
|
|
|
|
case 'u': // second from top of floating point stack.
|
|
|
|
|
return std::string("{st(1)}"); // second from top of floating point stack.
|
|
|
|
|
case 'Y':
|
|
|
|
|
switch (Constraint[1]) {
|
|
|
|
|
default:
|
|
|
|
|
// Break from inner switch and fall through (copy single char),
|
|
|
|
|
// continue parsing after copying the current constraint into
|
|
|
|
|
// the return string.
|
|
|
|
|
break;
|
|
|
|
|
case 'k':
|
2017-08-24 17:07:34 +08:00
|
|
|
case 'm':
|
|
|
|
|
case 'i':
|
|
|
|
|
case 't':
|
|
|
|
|
case 'z':
|
|
|
|
|
case '0':
|
|
|
|
|
case '2':
|
2017-07-22 06:37:03 +08:00
|
|
|
// "^" hints llvm that this is a 2 letter constraint.
|
|
|
|
|
// "Constraint++" is used to promote the string iterator
|
|
|
|
|
// to the next constraint.
|
|
|
|
|
return std::string("^") + std::string(Constraint++, 2);
|
|
|
|
|
}
|
|
|
|
|
LLVM_FALLTHROUGH;
|
|
|
|
|
default:
|
|
|
|
|
return std::string(1, *Constraint);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-24 00:20:15 +08:00
|
|
|
bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
|
|
|
|
|
// Perform any per-CPU checks necessary to determine if this CPU is
|
|
|
|
|
// acceptable.
|
|
|
|
|
switch (Kind) {
|
|
|
|
|
case CK_Generic:
|
|
|
|
|
// No processor selected!
|
|
|
|
|
return false;
|
2017-11-16 06:25:39 +08:00
|
|
|
#define PROC(ENUM, STRING, IS64BIT) \
|
|
|
|
|
case CK_##ENUM: \
|
|
|
|
|
return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
2017-10-24 00:20:15 +08:00
|
|
|
}
|
|
|
|
|
llvm_unreachable("Unhandled CPU kind");
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-09 07:15:02 +08:00
|
|
|
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
|
|
|
|
|
#define PROC(ENUM, STRING, IS64BIT) \
|
|
|
|
|
if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
|
|
|
|
|
Values.emplace_back(STRING);
|
|
|
|
|
// Go through CPUKind checking to ensure that the alias is de-aliased and
|
|
|
|
|
// 64 bit-ness is checked.
|
|
|
|
|
#define PROC_ALIAS(ENUM, ALIAS) \
|
|
|
|
|
if (checkCPUKind(getCPUKind(ALIAS))) \
|
|
|
|
|
Values.emplace_back(ALIAS);
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-22 06:37:03 +08:00
|
|
|
X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
|
|
|
|
|
return llvm::StringSwitch<CPUKind>(CPU)
|
2017-11-16 06:25:39 +08:00
|
|
|
#define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
|
|
|
|
|
#define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
|
|
|
|
|
#include "clang/Basic/X86Target.def"
|
2017-07-22 06:37:03 +08:00
|
|
|
.Default(CK_Generic);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
|
|
|
|
|
return llvm::makeArrayRef(GCCRegNames);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
|
|
|
|
|
return llvm::makeArrayRef(AddlRegNames);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
|
|
|
|
|
return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
|
|
|
|
|
Builtin::FirstTSBuiltin + 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
|
|
|
|
|
return llvm::makeArrayRef(BuiltinInfoX86,
|
|
|
|
|
X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
|
|
|
|
|
}
|