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llvm-project/llvm/test/CodeGen/X86/coal-sections.ll

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[MachO] Stop generating *coal* sections. Recommit r250342: move coal-sections-powerpc.s to subdirectory for powerpc. Some background on why we don't have to use *coal* sections anymore: Long ago when C++ was new and "weak" had not been standardized, an attempt was made in cctools to support C++ inlines that can be coalesced by putting them into their own section (TEXT/textcoal_nt instead of TEXT/text). The current macho linker supports the weak-def bit on any symbol to allow it to be coalesced, but the compiler still puts weak-def functions/data into alternate section names, which the linker must map back to the base section name. This patch makes changes that are necessary to prevent the compiler from using the "coal" sections and have it use the non-coal sections instead when the target architecture is not powerpc: TEXT/textcoal_nt instead use TEXT/text TEXT/const_coal instead use TEXT/const DATA/datacoal_nt instead use DATA/data If the target is powerpc, we continue to use the *coal* sections since anyone targeting powerpc is probably using an old linker that doesn't have support for the weak-def bits. Also, have the assembler issue a warning if it encounters a *coal* section in the assembly file and inform the users to use the non-coal sections instead. rdar://problem/14265330 Differential Revision: http://reviews.llvm.org/D13188 llvm-svn: 250370
2015-10-15 13:28:38 +08:00
; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s
; Check that *coal* sections are not emitted.
; CHECK: .section __TEXT,__text,regular,pure_instructions{{$}}
; CHECK-NEXT: .globl _foo
; CHECK: .section __TEXT,__const{{$}}
; CHECK-NEXT: .globl _a
; CHECK: .section __DATA,__data{{$}}
; CHECK-NEXT: .globl _b
@a = weak_odr constant [4 x i32] [i32 1, i32 2, i32 3, i32 4], align 16
@b = weak global i32 5, align 4
@g = common global i32* null, align 8
; Function Attrs: nounwind ssp uwtable
define weak i32* @foo() {
entry:
store i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i64 0, i64 0), i32** @g, align 8
ret i32* @b
}