maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/AVR/inst-or.s

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

20 lines
571 B
ArmAsm
Raw Normal View History

[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
[AVR] Disassemble register operands Simply by implementing a few functions I was able to correctly disassemble a much larger amount of instructions. Differential Revision: https://reviews.llvm.org/D74045
2020-02-05 19:53:06 +08:00
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
foo:
or r0, r15
or r15, r0
or r16, r31
or r31, r16
; CHECK: or r0, r15 ; encoding: [0x0f,0x28]
; CHECK: or r15, r0 ; encoding: [0xf0,0x28]
; CHECK: or r16, r31 ; encoding: [0x0f,0x2b]
; CHECK: or r31, r16 ; encoding: [0xf0,0x2b]
[AVR] Disassemble register operands Simply by implementing a few functions I was able to correctly disassemble a much larger amount of instructions. Differential Revision: https://reviews.llvm.org/D74045
2020-02-05 19:53:06 +08:00
; CHECK-INST: or r0, r15
; CHECK-INST: or r15, r0
; CHECK-INST: or r16, r31
; CHECK-INST: or r31, r16