2019-10-09 00:16:26 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2014-04-04 00:01:44 +08:00
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; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
|
2007-01-19 17:20:23 +08:00
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2011-03-19 05:52:42 +08:00
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define i32 @test1(i32 %X) nounwind {
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2019-10-09 00:16:26 +08:00
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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2010-10-23 05:55:03 +08:00
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%tmp1 = lshr i32 %X, 8
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%X15 = bitcast i32 %X to i32
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%tmp4 = shl i32 %X15, 8
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%tmp2 = and i32 %tmp1, 16711680
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%tmp5 = and i32 %tmp4, -16777216
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%tmp9 = and i32 %tmp1, 255
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%tmp13 = and i32 %tmp4, 65280
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%tmp6 = or i32 %tmp5, %tmp2
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%tmp10 = or i32 %tmp6, %tmp13
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%tmp14 = or i32 %tmp10, %tmp9
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2008-02-18 04:02:20 +08:00
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ret i32 %tmp14
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2007-01-19 17:20:23 +08:00
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|
}
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2011-03-19 05:52:42 +08:00
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define i32 @test2(i32 %X) nounwind {
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2019-10-09 00:16:26 +08:00
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: revsh r0, r0
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; CHECK-NEXT: bx lr
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2010-10-23 05:55:03 +08:00
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%tmp1 = lshr i32 %X, 8
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%tmp1.upgrd.1 = trunc i32 %tmp1 to i16
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%tmp3 = trunc i32 %X to i16
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%tmp2 = and i16 %tmp1.upgrd.1, 255
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%tmp4 = shl i16 %tmp3, 8
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%tmp5 = or i16 %tmp2, %tmp4
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%tmp5.upgrd.2 = sext i16 %tmp5 to i32
|
2008-02-18 04:02:20 +08:00
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|
ret i32 %tmp5.upgrd.2
|
2007-01-19 17:20:23 +08:00
|
|
|
}
|
2011-03-19 05:52:42 +08:00
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|
; rdar://9147637
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|
define i32 @test3(i16 zeroext %a) nounwind {
|
2013-07-14 04:38:47 +08:00
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|
; CHECK-LABEL: test3:
|
2019-10-09 00:16:26 +08:00
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|
; CHECK: @ %bb.0: @ %entry
|
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; CHECK-NEXT: revsh r0, r0
|
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|
; CHECK-NEXT: bx lr
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|
|
entry:
|
2011-03-19 05:52:42 +08:00
|
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|
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
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%1 = sext i16 %0 to i32
|
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|
ret i32 %1
|
|
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|
}
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|
|
declare i16 @llvm.bswap.i16(i16) nounwind readnone
|
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|
|
define i32 @test4(i16 zeroext %a) nounwind {
|
2013-07-14 04:38:47 +08:00
|
|
|
; CHECK-LABEL: test4:
|
2019-10-09 00:16:26 +08:00
|
|
|
; CHECK: @ %bb.0: @ %entry
|
|
|
|
; CHECK-NEXT: revsh r0, r0
|
|
|
|
; CHECK-NEXT: bx lr
|
|
|
|
entry:
|
2011-03-19 05:52:42 +08:00
|
|
|
%conv = zext i16 %a to i32
|
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|
%shr9 = lshr i16 %a, 8
|
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|
%conv2 = zext i16 %shr9 to i32
|
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|
%shl = shl nuw nsw i32 %conv, 8
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|
%or = or i32 %conv2, %shl
|
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|
%sext = shl i32 %or, 16
|
|
|
|
%conv8 = ashr exact i32 %sext, 16
|
|
|
|
ret i32 %conv8
|
|
|
|
}
|
2011-06-16 01:17:48 +08:00
|
|
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|
|
|
; rdar://9609059
|
|
|
|
define i32 @test5(i32 %i) nounwind readnone {
|
2019-10-09 00:16:26 +08:00
|
|
|
; CHECK-LABEL: test5:
|
|
|
|
; CHECK: @ %bb.0: @ %entry
|
|
|
|
; CHECK-NEXT: revsh r0, r0
|
|
|
|
; CHECK-NEXT: bx lr
|
2011-06-16 01:17:48 +08:00
|
|
|
entry:
|
|
|
|
%shl = shl i32 %i, 24
|
|
|
|
%shr = ashr exact i32 %shl, 16
|
|
|
|
%shr23 = lshr i32 %i, 8
|
|
|
|
%and = and i32 %shr23, 255
|
|
|
|
%or = or i32 %shr, %and
|
|
|
|
ret i32 %or
|
|
|
|
}
|
2011-06-18 04:47:21 +08:00
|
|
|
|
|
|
|
; rdar://9609108
|
|
|
|
define i32 @test6(i32 %x) nounwind readnone {
|
2019-10-09 00:16:26 +08:00
|
|
|
; CHECK-LABEL: test6:
|
|
|
|
; CHECK: @ %bb.0: @ %entry
|
|
|
|
; CHECK-NEXT: rev16 r0, r0
|
|
|
|
; CHECK-NEXT: bx lr
|
2011-06-18 04:47:21 +08:00
|
|
|
entry:
|
|
|
|
%and = shl i32 %x, 8
|
|
|
|
%shl = and i32 %and, 65280
|
|
|
|
%and2 = lshr i32 %x, 8
|
|
|
|
%shr11 = and i32 %and2, 255
|
|
|
|
%shr5 = and i32 %and2, 16711680
|
|
|
|
%shl9 = and i32 %and, -16777216
|
|
|
|
%or = or i32 %shr5, %shl9
|
|
|
|
%or6 = or i32 %or, %shr11
|
|
|
|
%or10 = or i32 %or6, %shl
|
|
|
|
ret i32 %or10
|
|
|
|
}
|
2011-06-21 14:01:08 +08:00
|
|
|
|
|
|
|
; rdar://9164521
|
|
|
|
define i32 @test7(i32 %a) nounwind readnone {
|
2019-10-09 00:16:26 +08:00
|
|
|
; CHECK-LABEL: test7:
|
|
|
|
; CHECK: @ %bb.0: @ %entry
|
|
|
|
; CHECK-NEXT: rev r0, r0
|
|
|
|
; CHECK-NEXT: lsr r0, r0, #16
|
|
|
|
; CHECK-NEXT: bx lr
|
2011-06-21 14:01:08 +08:00
|
|
|
entry:
|
|
|
|
%and = lshr i32 %a, 8
|
|
|
|
%shr3 = and i32 %and, 255
|
|
|
|
%and2 = shl i32 %a, 8
|
|
|
|
%shl = and i32 %and2, 65280
|
|
|
|
%or = or i32 %shr3, %shl
|
|
|
|
ret i32 %or
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @test8(i32 %a) nounwind readnone {
|
2019-10-09 00:16:26 +08:00
|
|
|
; CHECK-LABEL: test8:
|
|
|
|
; CHECK: @ %bb.0: @ %entry
|
|
|
|
; CHECK-NEXT: revsh r0, r0
|
|
|
|
; CHECK-NEXT: bx lr
|
2011-06-21 14:01:08 +08:00
|
|
|
entry:
|
|
|
|
%and = lshr i32 %a, 8
|
|
|
|
%shr4 = and i32 %and, 255
|
|
|
|
%and2 = shl i32 %a, 8
|
|
|
|
%or = or i32 %shr4, %and2
|
|
|
|
%sext = shl i32 %or, 16
|
|
|
|
%conv3 = ashr exact i32 %sext, 16
|
|
|
|
ret i32 %conv3
|
|
|
|
}
|
|
|
|
|
2012-02-23 10:58:19 +08:00
|
|
|
; rdar://10750814
|
2011-06-21 14:01:08 +08:00
|
|
|
define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {
|
2019-10-09 00:16:26 +08:00
|
|
|
; CHECK-LABEL: test9:
|
|
|
|
; CHECK: @ %bb.0: @ %entry
|
|
|
|
; CHECK-NEXT: rev16 r0, r0
|
|
|
|
; CHECK-NEXT: bx lr
|
2011-06-21 14:01:08 +08:00
|
|
|
entry:
|
|
|
|
%conv = zext i16 %v to i32
|
|
|
|
%shr4 = lshr i32 %conv, 8
|
|
|
|
%shl = shl nuw nsw i32 %conv, 8
|
|
|
|
%or = or i32 %shr4, %shl
|
|
|
|
%conv3 = trunc i32 %or to i16
|
|
|
|
ret i16 %conv3
|
|
|
|
}
|