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llvm-project/llvm/test/CodeGen/ARM/longMAC.ll

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ARM big endian function argument passing llvm-svn: 208316
2014-05-08 22:06:24 +08:00
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-V7-LE
ARM big endian function argument passing llvm-svn: 208316
2014-05-08 22:06:24 +08:00
; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7-BE
; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6-THUMB
; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP
; RUN: llc -mtriple=thumbebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7-THUMB-BE
; RUN: llc -mtriple=thumbv6m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6M-THUMB
; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7M-THUMB
; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP
; RUN: llc -mtriple=armv5te-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V5TE
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 22:37:49 +08:00
; Check generated signed and unsigned multiply accumulate long.
define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
;CHECK-LABEL: MACLongTest1:
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB-NOT: umlal
;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-LE: mov r0, [[RDLO]]
;CHECK-LE: mov r1, [[RDHI]]
;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-BE: mov r0, [[RDHI]]
;CHECK-BE: mov r1, [[RDLO]]
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]
;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]
[ARM] Predicate UMAAL selection on hasDSP. UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets. Also fix wrong CHECK prefix in longMAC.ll test. Patch by Vadzim Dambrouski. Differential Revision: https://reviews.llvm.org/D25890 llvm-svn: 285278
2016-10-27 17:47:10 +08:00
;CHECK-V7-THUMB-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 22:37:49 +08:00
%conv = zext i32 %a to i64
%conv1 = zext i32 %b to i64
%mul = mul i64 %conv1, %conv
%add = add i64 %mul, %c
ret i64 %add
}
define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
;CHECK-LABEL: MACLongTest2:
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-LE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-LE: mov r0, [[RDLO]]
;CHECK-LE: mov r1, [[RDHI]]
;CHECK-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-BE: mov r0, [[RDHI]]
;CHECK-BE: mov r1, [[RDLO]]
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]
;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]
[ARM] Predicate UMAAL selection on hasDSP. UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets. Also fix wrong CHECK prefix in longMAC.ll test. Patch by Vadzim Dambrouski. Differential Revision: https://reviews.llvm.org/D25890 llvm-svn: 285278
2016-10-27 17:47:10 +08:00
;CHECK-V7-THUMB-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 22:37:49 +08:00
%conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64
%mul = mul nsw i64 %conv1, %conv
%add = add nsw i64 %mul, %c
ret i64 %add
}
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.
; + Without @earlyclobber the v7 code is natural. With it, the first two
; registers must be distinct from the third.
; + Without "$Rd = $R", this can be satisfied without a mov before the umlal
; by trying to use 6 different registers in the MachineInstr. The natural
; evolution of this attempt currently leaves only two movs in the final
; function, both after the umlal. With it, *some* move has to happen
; before the umlal.
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 22:37:49 +08:00
define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
;CHECK-LABEL: MACLongTest3:
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-LE: mov [[RDHI:r[0-9]+]], #0
;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI]], r1, r0
;CHECK-LE: mov r0, [[RDLO]]
;CHECK-LE: mov r1, [[RDHI]]
;CHECK-BE: mov [[RDHI:r[0-9]+]], #0
;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI]], r1, r0
;CHECK-BE: mov r0, [[RDHI]]
;CHECK-BE: mov r1, [[RDLO]]
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: umlal
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB-NOT: umlal
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 22:37:49 +08:00
%conv = zext i32 %b to i64
%conv1 = zext i32 %a to i64
%mul = mul i64 %conv, %conv1
%conv2 = zext i32 %c to i64
%add = add i64 %mul, %conv2
ret i64 %add
}
define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
;CHECK-LABEL: MACLongTest4:
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB-NOT: smlal
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: smlal
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-LE: asr [[RDHI:r[0-9]+]], [[RDLO:r[0-9]+]], #31
;CHECK-LE: smlal [[RDLO]], [[RDHI]], r1, r0
;CHECK-LE: mov r0, [[RDLO]]
;CHECK-LE: mov r1, [[RDHI]]
;CHECK-BE: asr [[RDHI:r[0-9]+]], [[RDLO:r[0-9]+]], #31
;CHECK-BE: smlal [[RDLO]], [[RDHI]], r1, r0
;CHECK-BE: mov r0, [[RDHI]]
;CHECK-BE: mov r1, [[RDLO]]
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 22:37:49 +08:00
%conv = sext i32 %b to i64
%conv1 = sext i32 %a to i64
%mul = mul nsw i64 %conv, %conv1
%conv2 = sext i32 %c to i64
%add = add nsw i64 %mul, %conv2
ret i64 %add
}
ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts. llvm-svn: 199212
2014-01-14 21:05:47 +08:00
This patch fixes issue with lowering below mentioned pattern :- _foo: smull r0, r1, r1, r0 smull r2, r3, r3, r2 adds r0, r2, r0 adc r1, r3, r1 bx lr to _foo: smull r0, r1, r1, r0 smlal r0, r1, r3, r2 bx lr llvm-svn: 226904
2015-01-23 17:10:03 +08:00
define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {
;CHECK-LABEL: MACLongTest6:
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB-NOT: smull
;CHECK-V6-THUMB-NOT: smlal
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-LE: smull r12, lr, r1, r0
;CHECK-LE: smlal r12, lr, r3, r2
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V7: smull [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], r1, r0
;CHECK-V7: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: smull [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], r1, r0
;CHECK-T2-DSP: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]
This patch fixes issue with lowering below mentioned pattern :- _foo: smull r0, r1, r1, r0 smull r2, r3, r3, r2 adds r0, r2, r0 adc r1, r3, r1 bx lr to _foo: smull r0, r1, r1, r0 smlal r0, r1, r3, r2 bx lr llvm-svn: 226904
2015-01-23 17:10:03 +08:00
%conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64
%mul = mul nsw i64 %conv1, %conv
%conv2 = sext i32 %c to i64
%conv3 = sext i32 %d to i64
%mul4 = mul nsw i64 %conv3, %conv2
%add = add nsw i64 %mul4, %mul
ret i64 %add
}
define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) {
;CHECK-LABEL: MACLongTest7:
;CHECK-NOT: smlal
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB2-NOT: smlal
;CHECK-V7-THUMB-NOT: smlal
;CHECK-V6-THUMB-NOT: smlal
This patch fixes issue with lowering below mentioned pattern :- _foo: smull r0, r1, r1, r0 smull r2, r3, r3, r2 adds r0, r2, r0 adc r1, r3, r1 bx lr to _foo: smull r0, r1, r1, r0 smlal r0, r1, r3, r2 bx lr llvm-svn: 226904
2015-01-23 17:10:03 +08:00
%conv = sext i32 %lhs to i64
%conv1 = sext i32 %rhs to i64
%mul = mul nsw i64 %conv1, %conv
%shl = shl i64 %mul, 32
%shr = lshr i64 %mul, 32
%or = or i64 %shl, %shr
%add = add i64 %or, %acc
ret i64 %add
}
define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) {
;CHECK-LABEL: MACLongTest8:
;CHECK-NOT: smlal
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB2-NOT: smlal
;CHECK-V7-THUMB-NOT: smlal
;CHECK-V6-THUMB-NOT: smlal
This patch fixes issue with lowering below mentioned pattern :- _foo: smull r0, r1, r1, r0 smull r2, r3, r3, r2 adds r0, r2, r0 adc r1, r3, r1 bx lr to _foo: smull r0, r1, r1, r0 smlal r0, r1, r3, r2 bx lr llvm-svn: 226904
2015-01-23 17:10:03 +08:00
%conv = zext i32 %lhs to i64
%conv1 = zext i32 %rhs to i64
%mul = mul nuw i64 %conv1, %conv
%and = and i64 %mul, 4294967295
%shl = shl i64 %mul, 32
%or = or i64 %and, %shl
%add = add i64 %or, %acc
ret i64 %add
}
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-21 00:47:09 +08:00
define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
;CHECK-LABEL: MACLongTest9:
[ARM] Refactor Thumb2 Mul and Mla instr descs Recommitting after r274347 was reverted. This patch introduces some classes to refactor the 3 and 4 register Thumb2 multiplication instruction descriptions, plus improved tests for some of those instructions. Differential Revision: https://reviews.llvm.org/D21929 llvm-svn: 275979
2016-07-19 22:44:05 +08:00
;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-LE: mov r0, [[RDLO]]
;CHECK-V7-LE: mov r1, [[RDHI]]
;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-BE: mov r0, [[RDHI]]
;CHECK-V7-BE: mov r1, [[RDLO]]
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]
;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]
[ARM] Refactor Thumb2 Mul and Mla instr descs Recommitting after r274347 was reverted. This patch introduces some classes to refactor the 3 and 4 register Thumb2 multiplication instruction descriptions, plus improved tests for some of those instructions. Differential Revision: https://reviews.llvm.org/D21929 llvm-svn: 275979
2016-07-19 22:44:05 +08:00
;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-21 00:47:09 +08:00
;CHECK-NOT:umaal
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB-NOT: umaal
[ARM] Predicate UMAAL selection on hasDSP. UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets. Also fix wrong CHECK prefix in longMAC.ll test. Patch by Vadzim Dambrouski. Differential Revision: https://reviews.llvm.org/D25890 llvm-svn: 285278
2016-10-27 17:47:10 +08:00
;CHECK-V6M-THUMB-NOT: umaal
;CHECK-V7M-THUMB-NOT: umaal
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-21 00:47:09 +08:00
%conv = zext i32 %lhs to i64
%conv1 = zext i32 %rhs to i64
%mul = mul nuw i64 %conv1, %conv
%conv2 = zext i32 %lo to i64
%add = add i64 %mul, %conv2
%conv3 = zext i32 %hi to i64
%add2 = add i64 %add, %conv3
ret i64 %add2
}
define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
;CHECK-LABEL: MACLongTest10:
[ARM] Refactor Thumb2 Mul and Mla instr descs Recommitting after r274347 was reverted. This patch introduces some classes to refactor the 3 and 4 register Thumb2 multiplication instruction descriptions, plus improved tests for some of those instructions. Differential Revision: https://reviews.llvm.org/D21929 llvm-svn: 275979
2016-07-19 22:44:05 +08:00
;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-LE: mov r0, [[RDLO]]
;CHECK-V7-LE: mov r1, [[RDHI]]
;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-BE: mov r0, [[RDHI]]
;CHECK-V7-BE: mov r1, [[RDLO]]
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP: umaal r2, r3, r1, r0
;CHECK-T2-DSP-NEXT: mov r0, r2
;CHECK-T2-DSP-NEXT: mov r1, r3
[ARM] Refactor Thumb2 Mul and Mla instr descs Recommitting after r274347 was reverted. This patch introduces some classes to refactor the 3 and 4 register Thumb2 multiplication instruction descriptions, plus improved tests for some of those instructions. Differential Revision: https://reviews.llvm.org/D21929 llvm-svn: 275979
2016-07-19 22:44:05 +08:00
;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-21 00:47:09 +08:00
;CHECK-NOT:umaal
[ARM] Improve longMAC codegen test Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
2016-07-25 18:11:00 +08:00
;CHECK-V6-THUMB-NOT:umaal
[ARM] Predicate UMAAL selection on hasDSP. UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets. Also fix wrong CHECK prefix in longMAC.ll test. Patch by Vadzim Dambrouski. Differential Revision: https://reviews.llvm.org/D25890 llvm-svn: 285278
2016-10-27 17:47:10 +08:00
;CHECK-V6M-THUMB-NOT: umaal
;CHECK-V7M-THUMB-NOT: umaal
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-21 00:47:09 +08:00
%conv = zext i32 %lhs to i64
%conv1 = zext i32 %rhs to i64
[ARM] Add newline char to test. Missed a newline in the previous commit. Differential Revision: https://reviews.llvm.org/D26027 llvm-svn: 285280
2016-10-27 18:43:02 +08:00
%mul = mul nuw i64 %conv1, %conv
%conv2 = zext i32 %lo to i64
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-21 00:47:09 +08:00
%conv3 = zext i32 %hi to i64
%add = add i64 %conv2, %conv3
%add2 = add i64 %add, %mul
ret i64 %add2
}
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
define i64 @MACLongTest11(i16 %a, i16 %b, i64 %c) {
;CHECK-LABEL: MACLongTest11:
;CHECK-T2-DSP-NOT: sxth
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-T2-DSP: smlalbb r2, r3
;CHECK-T2-DSP-NEXT: mov r0, r2
;CHECK-T2-DSP-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V5TE-NOT: sxth
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V5TE: smlalbb r2, r3
;CHECK-V5TE-NEXT: mov r0, r2
;CHECK-V5TE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V7-LE-NOT: sxth
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-LE: smlalbb r2, r3
;CHECK-V7-LE-NEXT: mov r0, r2
;CHECK-V7-LE-NEXT: mov r1, r3
;CHECK-V7-THUMB-BE: smlalbb r3, r2
;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-LE-NOT: smlalbb
;CHECK-BE-NOT: smlalbb
;CHECK-V6M-THUMB-NOT: smlalbb
;CHECK-V7M-THUMB-NOT: smlalbb
%conv = sext i16 %a to i32
%conv1 = sext i16 %b to i32
%mul = mul nsw i32 %conv1, %conv
%conv2 = sext i32 %mul to i64
%add = add nsw i64 %conv2, %c
ret i64 %add
}
define i64 @MACLongTest12(i16 %b, i32 %t, i64 %c) {
;CHECK-LABEL: MACLongTest12:
;CHECK-T2-DSP-NOT: sxth
;CHECK-T2-DSP-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-T2-DSP: smlalbt r2, r3, r0, r1
;CHECK-T2-DSP-NEXT: mov r0, r2
;CHECK-T2-DSP-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-T2-DSP-NOT: sxth
;CHECK-V5TE-NOT: sxth
;CHECK-V5TE-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V5TE: smlalbt r2, r3, r0, r1
;CHECK-V5TE-NEXT: mov r0, r2
;CHECK-V5TE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V7-LE-NOT: sxth
;CHECK-V7-LE-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-LE: smlalbt r2, r3, r0, r1
;CHECK-V7-LE-NEXT: mov r0, r2
;CHECK-V7-LE-NEXT: mov r1, r3
;CHECK-V7-THUMB-BE: smlalbt r3, r2,
;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-LE-NOT: smlalbt
;CHECK-BE-NOT: smlalbt
;CHECK-V6M-THUMB-NOT: smlalbt
;CHECK-V7M-THUMB-NOT: smlalbt
%conv0 = sext i16 %b to i32
%conv1 = ashr i32 %t, 16
%mul = mul nsw i32 %conv0, %conv1
%conv2 = sext i32 %mul to i64
%add = add nsw i64 %conv2, %c
ret i64 %add
}
define i64 @MACLongTest13(i32 %t, i16 %b, i64 %c) {
;CHECK-LABEL: MACLongTest13:
;CHECK-T2-DSP-NOT: sxth
;CHECK-T2-DSP-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-T2-DSP: smlaltb r2, r3, r0, r1
;CHECK-T2-DSP-NEXT: mov r0, r2
;CHECK-T2-DSP-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V5TE-NOT: sxth
;CHECK-V5TE-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V5TE: smlaltb r2, r3, r0, r1
;CHECK-V5TE-NEXT: mov r0, r2
;CHECK-V5TE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V7-LE-NOT: sxth
;CHECK-V7-LE-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-LE: smlaltb r2, r3, r0, r1
;CHECK-V7-LE-NEXT: mov r0, r2
;CHECK-V7-LE-NEXT: mov r1, r3
;CHECK-V7-THUMB-BE: smlaltb r3, r2, r0, r1
;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-LE-NOT: smlaltb
;CHECK-BE-NOT: smlaltb
;CHECK-V6M-THUMB-NOT: smlaltb
;CHECK-V7M-THUMB-NOT: smlaltb
%conv0 = ashr i32 %t, 16
%conv1= sext i16 %b to i32
%mul = mul nsw i32 %conv0, %conv1
%conv2 = sext i32 %mul to i64
%add = add nsw i64 %conv2, %c
ret i64 %add
}
define i64 @MACLongTest14(i32 %a, i32 %b, i64 %c) {
;CHECK-LABEL: MACLongTest14:
;CHECK-T2-DSP-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-T2-DSP: smlaltt r2, r3,
;CHECK-T2-DSP-NEXT: mov r0, r2
;CHECK-T2-DSP-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V5TE-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V5TE: smlaltt r2, r3,
;CHECK-V5TE-NEXT: mov r0, r2
;CHECK-V5TE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V7-LE-NOT: {{asr|lsr}}
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-LE: smlaltt r2, r3,
;CHECK-V7-LE-NEXT: mov r0, r2
;CHECK-V7-LE-NEXT: mov r1, r3
;CHECK-V7-THUMB-BE: smlaltt r3, r2,
;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-LE-NOT: smlaltt
;CHECK-BE-NOT: smlaltt
;CHECK-V6M-THUMB-NOT: smlaltt
;CHECK-V7M-THUMB-NOT: smlaltt
%conv0 = ashr i32 %a, 16
%conv1 = ashr i32 %b, 16
%mul = mul nsw i32 %conv1, %conv0
%conv2 = sext i32 %mul to i64
%add = add nsw i64 %conv2, %c
ret i64 %add
}
@global_b = external global i16, align 2
;CHECK-LABEL: MACLongTest15
;CHECK-T2-DSP-NOT: {{asr|lsr}}
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-T2-DSP: mov r1, r3
;CHECK-T2-DSP: smlaltb r2, r1, r0, r3
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-T2-DSP-NEXT: mov r0, r2
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V5TE-NOT: {{asr|lsr}}
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-V5TE: mov r1, r3
;CHECK-V5TE: smlaltb r2, r1, r0, r3
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V5TE-NEXT: mov r0, r2
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V7-LE-NOT: {{asr|lsr}}
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-V7-LE: mov r1, r3
;CHECK-V7-LE: smlaltb r2, r1, r0, r3
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-LE-NEXT: mov r0, r2
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-V7-THUMB-BE: mov r1, r3
;CHECK-V7-THUMB-BE: smlaltb r1, r2, r0, r3
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-LE-NOT: smlaltb
;CHECK-BE-NOT: smlaltb
;CHECK-V6M-THUMB-NOT: smlaltb
;CHECK-V7M-THUMB-NOT: smlaltb
define i64 @MACLongTest15(i32 %t, i64 %acc) {
entry:
%0 = load i16, i16* @global_b, align 2
%conv = sext i16 %0 to i32
%shr = ashr i32 %t, 16
%mul = mul nsw i32 %shr, %conv
%conv1 = sext i32 %mul to i64
%add = add nsw i64 %conv1, %acc
ret i64 %add
}
;CHECK-LABEL: MACLongTest16
;CHECK-T2-DSP-NOT: {{asr|lsr}}
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-T2-DSP: mov r1, r3
;CHECK-T2-DSP: smlalbt r2, r1, r3, r0
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-T2-DSP-NEXT: mov r0, r2
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-V5TE-NOT: {{asr|lsr}}
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-V5TE: mov r1, r3
;CHECK-V5TE: smlalbt r2, r1, r3, r0
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V5TE-NEXT: mov r0, r2
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-V7-LE: mov r1, r3
;CHECK-V7-LE: smlalbt r2, r1, r3, r0
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-LE-NEXT: mov r0, r2
[ARM] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
2018-02-16 17:51:01 +08:00
;CHECK-V7-THUMB-BE: mov r1, r3
;CHECK-V7-THUMB-BE: smlalbt r1, r2, r3, r0
[ARM] Fix mixup between Lo and Hi in SMLALBB formation. llvm-svn: 298752
2017-03-25 08:13:24 +08:00
;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 16:27:11 +08:00
;CHECK-LE-NOT: smlalbt
;CHECK-BE-NOT: smlalbt
;CHECK-V6M-THUMB-NOT: smlalbt
;CHECK-V7M-THUMB-NOT: smlalbt
define i64 @MACLongTest16(i32 %t, i64 %acc) {
entry:
%0 = load i16, i16* @global_b, align 2
%conv = sext i16 %0 to i32
%shr = ashr i32 %t, 16
%mul = mul nsw i32 %conv, %shr
%conv1 = sext i32 %mul to i64
%add = add nsw i64 %conv1, %acc
ret i64 %add
}