[libomptarget][nfc] Move omptarget-nvptx under common
Summary:
[libomptarget][nfc] Move omptarget-nvptx under common
Almost all files depend on require omptarget-nvptx, which no longer
contains any obviously architecture dependent code. Moving it under
common unblocks task/loop for amdgcn, and allows moving other code.
At some point there should probably be a widespread symbol renaming to
replace the nvptx string. I'd prefer to get things working first.
Building this (and task.cu, loop.cu) without a cuda library requires
some more refactoring, e.g. wrap threadfence(), use DEVICE macro more
consistently. Patches for that are orthogonal and will be posted shortly.
Reviewers: jdoerfert, ABataev, grokos
Reviewed By: ABataev
Subscribers: mgorny, fedor.sergeev, jfb, openmp-commits
Tags: #openmp
Differential Revision: https://reviews.llvm.org/D71073
2019-12-06 04:34:14 +08:00
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//===---- omptarget.h - OpenMP GPU initialization ---------------- CUDA -*-===//
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2018-01-29 21:59:35 +08:00
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//
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2019-01-19 18:56:40 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-01-29 21:59:35 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declarations of all library macros, types,
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// and functions.
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//
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//===----------------------------------------------------------------------===//
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[libomptarget][nfc] Move omptarget-nvptx under common
Summary:
[libomptarget][nfc] Move omptarget-nvptx under common
Almost all files depend on require omptarget-nvptx, which no longer
contains any obviously architecture dependent code. Moving it under
common unblocks task/loop for amdgcn, and allows moving other code.
At some point there should probably be a widespread symbol renaming to
replace the nvptx string. I'd prefer to get things working first.
Building this (and task.cu, loop.cu) without a cuda library requires
some more refactoring, e.g. wrap threadfence(), use DEVICE macro more
consistently. Patches for that are orthogonal and will be posted shortly.
Reviewers: jdoerfert, ABataev, grokos
Reviewed By: ABataev
Subscribers: mgorny, fedor.sergeev, jfb, openmp-commits
Tags: #openmp
Differential Revision: https://reviews.llvm.org/D71073
2019-12-06 04:34:14 +08:00
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#ifndef OMPTARGET_H
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#define OMPTARGET_H
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2018-01-29 21:59:35 +08:00
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[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
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#include "common/allocator.h"
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#include "common/debug.h" // debug
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2019-11-19 02:16:35 +08:00
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#include "common/state-queue.h"
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2019-12-05 00:43:16 +08:00
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#include "common/support.h"
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[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
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#include "interface.h" // interfaces with omp, compiler, and user
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#include "target_impl.h"
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2018-01-29 21:59:35 +08:00
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#define OMPTARGET_NVPTX_VERSION 1.1
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// used by the library for the interface with the app
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#define DISPATCH_FINISHED 0
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#define DISPATCH_NOTFINISHED 1
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// used by dynamic scheduling
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#define FINISHED 0
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#define NOT_FINISHED 1
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#define LAST_CHUNK 2
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#define BARRIER_COUNTER 0
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#define ORDERED_COUNTER 1
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2020-12-11 10:13:22 +08:00
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// Worker slot type which is initialized with the default worker slot
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// size of 4*32 bytes.
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struct __kmpc_data_sharing_slot {
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__kmpc_data_sharing_slot *Next;
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__kmpc_data_sharing_slot *Prev;
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void *PrevSlotStackPtr;
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void *DataEnd;
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char Data[DS_Worker_Warp_Slot_Size];
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};
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2018-01-29 21:59:35 +08:00
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////////////////////////////////////////////////////////////////////////////////
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// task ICV and (implicit & explicit) task state
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class omptarget_nvptx_TaskDescr {
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public:
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// methods for flags
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2019-01-05 04:16:54 +08:00
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INLINE omp_sched_t GetRuntimeSched() const;
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2018-01-29 21:59:35 +08:00
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INLINE void SetRuntimeSched(omp_sched_t sched);
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2019-01-05 04:16:54 +08:00
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INLINE int InParallelRegion() const { return items.flags & TaskDescr_InPar; }
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INLINE int InL2OrHigherParallelRegion() const {
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2018-03-09 02:44:02 +08:00
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return items.flags & TaskDescr_InParL2P;
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2018-01-29 21:59:35 +08:00
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}
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2019-01-05 04:16:54 +08:00
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INLINE int IsParallelConstruct() const {
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2018-03-09 02:44:02 +08:00
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return items.flags & TaskDescr_IsParConstr;
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2018-01-29 21:59:35 +08:00
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}
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2019-01-05 04:16:54 +08:00
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INLINE int IsTaskConstruct() const { return !IsParallelConstruct(); }
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2018-01-29 21:59:35 +08:00
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// methods for other fields
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2018-03-09 02:44:02 +08:00
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INLINE uint16_t &ThreadId() { return items.threadId; }
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INLINE uint64_t &RuntimeChunkSize() { return items.runtimeChunkSize; }
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2019-01-05 04:16:54 +08:00
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INLINE omptarget_nvptx_TaskDescr *GetPrevTaskDescr() const { return prev; }
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2018-01-29 21:59:35 +08:00
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INLINE void SetPrevTaskDescr(omptarget_nvptx_TaskDescr *taskDescr) {
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prev = taskDescr;
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}
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// init & copy
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2019-05-13 22:21:46 +08:00
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INLINE void InitLevelZeroTaskDescr();
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2019-05-11 02:56:05 +08:00
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INLINE void InitLevelOneTaskDescr(omptarget_nvptx_TaskDescr *parentTaskDescr);
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2018-01-29 21:59:35 +08:00
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INLINE void Copy(omptarget_nvptx_TaskDescr *sourceTaskDescr);
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INLINE void CopyData(omptarget_nvptx_TaskDescr *sourceTaskDescr);
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INLINE void CopyParent(omptarget_nvptx_TaskDescr *parentTaskDescr);
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INLINE void CopyForExplicitTask(omptarget_nvptx_TaskDescr *parentTaskDescr);
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2019-05-11 02:56:05 +08:00
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INLINE void CopyToWorkDescr(omptarget_nvptx_TaskDescr *masterTaskDescr);
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2018-01-29 21:59:35 +08:00
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INLINE void CopyFromWorkDescr(omptarget_nvptx_TaskDescr *workTaskDescr);
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INLINE void CopyConvergentParent(omptarget_nvptx_TaskDescr *parentTaskDescr,
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uint16_t tid, uint16_t tnum);
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2018-07-12 23:18:28 +08:00
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INLINE void SaveLoopData();
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INLINE void RestoreLoopData() const;
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2018-01-29 21:59:35 +08:00
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private:
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2018-09-30 00:02:25 +08:00
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// bits for flags: (6 used, 2 free)
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2018-01-29 21:59:35 +08:00
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// 3 bits (SchedMask) for runtime schedule
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// 1 bit (InPar) if this thread has encountered one or more parallel region
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// 1 bit (IsParConstr) if ICV for a parallel region (false = explicit task)
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// 1 bit (InParL2+) if this thread has encountered L2 or higher parallel
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// region
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static const uint8_t TaskDescr_SchedMask = (0x1 | 0x2 | 0x4);
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static const uint8_t TaskDescr_InPar = 0x10;
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static const uint8_t TaskDescr_IsParConstr = 0x20;
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static const uint8_t TaskDescr_InParL2P = 0x40;
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2018-07-12 23:18:28 +08:00
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struct SavedLoopDescr_items {
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int64_t loopUpperBound;
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int64_t nextLowerBound;
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int64_t chunk;
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int64_t stride;
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kmp_sched_t schedule;
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} loopData;
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2018-03-09 02:44:02 +08:00
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struct TaskDescr_items {
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uint8_t flags; // 6 bit used (see flag above)
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uint8_t unused;
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uint16_t threadId; // thread id
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uint64_t runtimeChunkSize; // runtime chunk size
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} items;
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2018-01-29 21:59:35 +08:00
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omptarget_nvptx_TaskDescr *prev;
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};
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// build on kmp
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typedef struct omptarget_nvptx_ExplicitTaskDescr {
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omptarget_nvptx_TaskDescr
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taskDescr; // omptarget_nvptx task description (must be first)
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kmp_TaskDescr kmpTaskDescr; // kmp task description (must be last)
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} omptarget_nvptx_ExplicitTaskDescr;
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////////////////////////////////////////////////////////////////////////////////
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// Descriptor of a parallel region (worksharing in general)
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class omptarget_nvptx_WorkDescr {
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public:
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// access to data
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INLINE omptarget_nvptx_TaskDescr *WorkTaskDescr() { return &masterTaskICV; }
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private:
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omptarget_nvptx_TaskDescr masterTaskICV;
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};
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////////////////////////////////////////////////////////////////////////////////
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class omptarget_nvptx_TeamDescr {
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public:
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// access to data
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INLINE omptarget_nvptx_TaskDescr *LevelZeroTaskDescr() {
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return &levelZeroTaskDescr;
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}
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INLINE omptarget_nvptx_WorkDescr &WorkDescr() {
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return workDescrForActiveParallel;
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}
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// init
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2019-05-13 22:21:46 +08:00
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INLINE void InitTeamDescr();
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2018-01-29 21:59:35 +08:00
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2018-07-14 00:14:22 +08:00
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INLINE __kmpc_data_sharing_slot *GetPreallocatedSlotAddr(int wid) {
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worker_rootS[wid].DataEnd =
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&worker_rootS[wid].Data[0] + DS_Worker_Warp_Slot_Size;
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// We currently do not have a next slot.
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worker_rootS[wid].Next = 0;
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worker_rootS[wid].Prev = 0;
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worker_rootS[wid].PrevSlotStackPtr = 0;
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return (__kmpc_data_sharing_slot *)&worker_rootS[wid];
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}
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2018-01-29 21:59:35 +08:00
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private:
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omptarget_nvptx_TaskDescr
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levelZeroTaskDescr; // icv for team master initial thread
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omptarget_nvptx_WorkDescr
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workDescrForActiveParallel; // one, ONLY for the active par
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2019-12-06 05:47:43 +08:00
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ALIGN(16)
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2020-12-11 10:13:22 +08:00
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__kmpc_data_sharing_slot worker_rootS[DS_Max_Warp_Number];
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2018-01-29 21:59:35 +08:00
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};
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////////////////////////////////////////////////////////////////////////////////
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// thread private data (struct of arrays for better coalescing)
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// tid refers here to the global thread id
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// do not support multiple concurrent kernel a this time
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class omptarget_nvptx_ThreadPrivateContext {
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public:
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// task
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INLINE omptarget_nvptx_TaskDescr *Level1TaskDescr(int tid) {
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return &levelOneTaskDescr[tid];
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}
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INLINE void SetTopLevelTaskDescr(int tid,
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omptarget_nvptx_TaskDescr *taskICV) {
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topTaskDescr[tid] = taskICV;
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}
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2019-01-05 04:16:54 +08:00
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INLINE omptarget_nvptx_TaskDescr *GetTopLevelTaskDescr(int tid) const;
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2018-01-29 21:59:35 +08:00
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// schedule (for dispatch)
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INLINE kmp_sched_t &ScheduleType(int tid) { return schedule[tid]; }
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INLINE int64_t &Chunk(int tid) { return chunk[tid]; }
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INLINE int64_t &LoopUpperBound(int tid) { return loopUpperBound[tid]; }
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2018-07-12 23:18:28 +08:00
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INLINE int64_t &NextLowerBound(int tid) { return nextLowerBound[tid]; }
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INLINE int64_t &Stride(int tid) { return stride[tid]; }
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2018-01-29 21:59:35 +08:00
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INLINE omptarget_nvptx_TeamDescr &TeamContext() { return teamContext; }
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INLINE void InitThreadPrivateContext(int tid);
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2019-01-07 22:25:25 +08:00
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INLINE uint64_t &Cnt() { return cnt; }
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2018-01-29 21:59:35 +08:00
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private:
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// team context for this team
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omptarget_nvptx_TeamDescr teamContext;
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2020-01-07 14:03:31 +08:00
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// task ICV for implicit threads in the only parallel region
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2018-01-29 21:59:35 +08:00
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omptarget_nvptx_TaskDescr levelOneTaskDescr[MAX_THREADS_PER_TEAM];
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// pointer where to find the current task ICV (top of the stack)
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omptarget_nvptx_TaskDescr *topTaskDescr[MAX_THREADS_PER_TEAM];
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// schedule (for dispatch)
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kmp_sched_t schedule[MAX_THREADS_PER_TEAM]; // remember schedule type for #for
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int64_t chunk[MAX_THREADS_PER_TEAM];
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int64_t loopUpperBound[MAX_THREADS_PER_TEAM];
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// state for dispatch with dyn/guided OR static (never use both at a time)
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2018-07-12 23:18:28 +08:00
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int64_t nextLowerBound[MAX_THREADS_PER_TEAM];
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int64_t stride[MAX_THREADS_PER_TEAM];
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2019-01-07 22:25:25 +08:00
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uint64_t cnt;
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2018-01-29 21:59:35 +08:00
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};
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2018-11-02 22:43:23 +08:00
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/// Memory manager for statically allocated memory.
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class omptarget_nvptx_SimpleMemoryManager {
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private:
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[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
|
|
|
struct MemDataTy {
|
2018-11-02 22:43:23 +08:00
|
|
|
volatile unsigned keys[OMP_STATE_COUNT];
|
[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
|
|
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} MemData[MAX_SM] ALIGN(128);
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2018-11-02 22:43:23 +08:00
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2019-01-05 04:16:54 +08:00
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INLINE static uint32_t hash(unsigned key) {
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2018-11-02 22:43:23 +08:00
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return key & (OMP_STATE_COUNT - 1);
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}
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public:
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INLINE void Release();
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INLINE const void *Acquire(const void *buf, size_t size);
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};
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2018-05-05 03:29:28 +08:00
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////////////////////////////////////////////////////////////////////////////////
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2018-01-29 21:59:35 +08:00
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////////////////////////////////////////////////////////////////////////////////
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// global data tables
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////////////////////////////////////////////////////////////////////////////////
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2021-03-16 04:12:49 +08:00
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extern omptarget_nvptx_SimpleMemoryManager omptarget_nvptx_simpleMemoryManager;
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extern uint32_t EXTERN_SHARED(usedMemIdx);
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extern uint32_t EXTERN_SHARED(usedSlotIdx);
|
[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
|
|
|
#if _OPENMP
|
2021-03-16 04:12:49 +08:00
|
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|
extern uint8_t parallelLevel[MAX_THREADS_PER_TEAM / WARPSIZE];
|
[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
|
|
|
#pragma omp allocate(parallelLevel) allocator(omp_pteam_mem_alloc)
|
|
|
|
#else
|
2021-03-16 04:12:49 +08:00
|
|
|
extern uint8_t EXTERN_SHARED(parallelLevel)[MAX_THREADS_PER_TEAM / WARPSIZE];
|
[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
|
|
|
#endif
|
2021-03-16 04:12:49 +08:00
|
|
|
extern uint16_t EXTERN_SHARED(threadLimit);
|
|
|
|
extern uint16_t EXTERN_SHARED(threadsInTeam);
|
|
|
|
extern uint16_t EXTERN_SHARED(nThreads);
|
|
|
|
extern omptarget_nvptx_ThreadPrivateContext *
|
[OpenMP][deviceRTLs] Build the deviceRTLs with OpenMP instead of target dependent language
From this patch (plus some landed patches), `deviceRTLs` is taken as a regular OpenMP program with just `declare target` regions. In this way, ideally, `deviceRTLs` can be written in OpenMP directly. No CUDA, no HIP anymore. (Well, AMD is still working on getting it work. For now AMDGCN still uses original way to compile) However, some target specific functions are still required, but they're no longer written in target specific language. For example, CUDA parts have all refined by replacing CUDA intrinsic and builtins with LLVM/Clang/NVVM intrinsics.
Here're a list of changes in this patch.
1. For NVPTX, `DEVICE` is defined empty in order to make the common parts still work with AMDGCN. Later once AMDGCN is also available, we will completely remove `DEVICE` or probably some other macros.
2. Shared variable is implemented with OpenMP allocator, which is defined in `allocator.h`. Again, this feature is not available on AMDGCN, so two macros are redefined properly.
3. CUDA header `cuda.h` is dropped in the source code. In order to deal with code difference in various CUDA versions, we build one bitcode library for each supported CUDA version. For each CUDA version, the highest PTX version it supports will be used, just as what we currently use for CUDA compilation.
4. Correspondingly, compiler driver is also updated to support CUDA version encoded in the name of bitcode library. Now the bitcode library for NVPTX is named as `libomptarget-nvptx-cuda_[cuda_version]-sm_[sm_number].bc`, such as `libomptarget-nvptx-cuda_80-sm_20.bc`.
With this change, there are also multiple features to be expected in the near future:
1. CUDA will be completely dropped when compiling OpenMP. By the time, we also build bitcode libraries for all supported SM, multiplied by all supported CUDA version.
2. Atomic operations used in `deviceRTLs` can be replaced by `omp atomic` if OpenMP 5.1 feature is fully supported. For now, the IR generated is totally wrong.
3. Target specific parts will be wrapped into `declare variant` with `isa` selector if it can work properly. No target specific macro is needed anymore.
4. (Maybe more...)
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D94745
2021-01-27 01:28:15 +08:00
|
|
|
EXTERN_SHARED(omptarget_nvptx_threadPrivateContext);
|
|
|
|
|
2021-09-23 05:16:28 +08:00
|
|
|
extern int8_t EXTERN_SHARED(execution_param);
|
2021-03-16 04:12:49 +08:00
|
|
|
extern void *EXTERN_SHARED(ReductionScratchpadPtr);
|
2018-01-29 21:59:35 +08:00
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// work function (outlined parallel/simd functions) and arguments.
|
|
|
|
// needed for L1 parallelism only.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
typedef void *omptarget_nvptx_WorkFn;
|
2021-07-20 04:54:31 +08:00
|
|
|
extern omptarget_nvptx_WorkFn EXTERN_SHARED(omptarget_nvptx_workFn);
|
2018-01-29 21:59:35 +08:00
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// get private data structures
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
INLINE omptarget_nvptx_TeamDescr &getMyTeamDescriptor();
|
|
|
|
INLINE omptarget_nvptx_WorkDescr &getMyWorkDescriptor();
|
2019-01-05 01:09:12 +08:00
|
|
|
INLINE omptarget_nvptx_TaskDescr *
|
|
|
|
getMyTopTaskDescriptor(bool isSPMDExecutionMode);
|
2018-01-29 21:59:35 +08:00
|
|
|
INLINE omptarget_nvptx_TaskDescr *getMyTopTaskDescriptor(int globalThreadId);
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// inlined implementation
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2021-01-28 21:14:21 +08:00
|
|
|
INLINE uint32_t __kmpc_impl_ffs(uint32_t x) { return __builtin_ffs(x); }
|
|
|
|
INLINE uint32_t __kmpc_impl_popc(uint32_t x) { return __builtin_popcount(x); }
|
2021-02-12 17:51:21 +08:00
|
|
|
INLINE uint32_t __kmpc_impl_ffs(uint64_t x) { return __builtin_ffsl(x); }
|
|
|
|
INLINE uint32_t __kmpc_impl_popc(uint64_t x) { return __builtin_popcountl(x); }
|
2021-01-28 21:14:21 +08:00
|
|
|
|
[libomptarget][nfc] Move omptarget-nvptx under common
Summary:
[libomptarget][nfc] Move omptarget-nvptx under common
Almost all files depend on require omptarget-nvptx, which no longer
contains any obviously architecture dependent code. Moving it under
common unblocks task/loop for amdgcn, and allows moving other code.
At some point there should probably be a widespread symbol renaming to
replace the nvptx string. I'd prefer to get things working first.
Building this (and task.cu, loop.cu) without a cuda library requires
some more refactoring, e.g. wrap threadfence(), use DEVICE macro more
consistently. Patches for that are orthogonal and will be posted shortly.
Reviewers: jdoerfert, ABataev, grokos
Reviewed By: ABataev
Subscribers: mgorny, fedor.sergeev, jfb, openmp-commits
Tags: #openmp
Differential Revision: https://reviews.llvm.org/D71073
2019-12-06 04:34:14 +08:00
|
|
|
#include "common/omptargeti.h"
|
2018-01-29 21:59:35 +08:00
|
|
|
|
|
|
|
#endif
|