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llvm-project/llvm/test/CodeGen/PowerPC/signbit-shift.ll

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[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC llvm-svn: 336348
2018-07-05 21:16:46 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
; If positive...
define i32 @zext_ifpos(i32 %x) {
; CHECK-LABEL: zext_ifpos:
; CHECK: # %bb.0:
; CHECK-NEXT: nor 3, 3, 3
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%e = zext i1 %c to i32
ret i32 %e
}
define i32 @add_zext_ifpos(i32 %x) {
; CHECK-LABEL: add_zext_ifpos:
; CHECK: # %bb.0:
[DAGCombiner] fold 'not' with signbit math This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
2018-07-28 00:42:55 +08:00
; CHECK-NEXT: srawi 3, 3, 31
; CHECK-NEXT: addi 3, 3, 42
[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC llvm-svn: 336348
2018-07-05 21:16:46 +08:00
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%e = zext i1 %c to i32
%r = add i32 %e, 41
ret i32 %r
}
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_zext_ifpos_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisb 3, -1
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-NEXT: vcmpgtsw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vsubuwm 2, 3, 2
; CHECK-NEXT: blr
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = zext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
ret <4 x i32> %r
}
[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC llvm-svn: 336348
2018-07-05 21:16:46 +08:00
define i32 @sel_ifpos_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 42, i32 41
ret i32 %r
}
define i32 @sext_ifpos(i32 %x) {
; CHECK-LABEL: sext_ifpos:
; CHECK: # %bb.0:
; CHECK-NEXT: nor 3, 3, 3
; CHECK-NEXT: srawi 3, 3, 31
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%e = sext i1 %c to i32
ret i32 %e
}
define i32 @add_sext_ifpos(i32 %x) {
; CHECK-LABEL: add_sext_ifpos:
; CHECK: # %bb.0:
; CHECK-NEXT: nor 3, 3, 3
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
2018-07-16 00:27:07 +08:00
; CHECK-NEXT: srawi 3, 3, 31
[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC llvm-svn: 336348
2018-07-05 21:16:46 +08:00
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%e = sext i1 %c to i32
%r = add i32 %e, 42
ret i32 %r
}
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_sext_ifpos_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisb 3, -1
; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-NEXT: vcmpgtsw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r
}
[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC llvm-svn: 336348
2018-07-05 21:16:46 +08:00
define i32 @sel_ifpos_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 41, i32 42
ret i32 %r
}
; If negative...
define i32 @zext_ifneg(i32 %x) {
; CHECK-LABEL: zext_ifneg:
; CHECK: # %bb.0:
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0
%r = zext i1 %c to i32
ret i32 %r
}
define i32 @add_zext_ifneg(i32 %x) {
; CHECK-LABEL: add_zext_ifneg:
; CHECK: # %bb.0:
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: addi 3, 3, 41
; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0
%e = zext i1 %c to i32
%r = add i32 %e, 41
ret i32 %r
}
define i32 @sel_ifneg_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_tval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0
%r = select i1 %c, i32 42, i32 41
ret i32 %r
}
define i32 @sext_ifneg(i32 %x) {
; CHECK-LABEL: sext_ifneg:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0
%r = sext i1 %c to i32
ret i32 %r
}
define i32 @add_sext_ifneg(i32 %x) {
; CHECK-LABEL: add_sext_ifneg:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0
%e = sext i1 %c to i32
%r = add i32 %e, 42
ret i32 %r
}
define i32 @sel_ifneg_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_fval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0
%r = select i1 %c, i32 41, i32 42
ret i32 %r
}
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
define i32 @add_lshr_not(i32 %x) {
; CHECK-LABEL: add_lshr_not:
; CHECK: # %bb.0:
[DAGCombiner] fold 'not' with signbit math This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
2018-07-28 00:42:55 +08:00
; CHECK-NEXT: srawi 3, 3, 31
; CHECK-NEXT: addi 3, 3, 42
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
; CHECK-NEXT: blr
%not = xor i32 %x, -1
%sh = lshr i32 %not, 31
%r = add i32 %sh, 41
ret i32 %r
}
define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_lshr_not_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l
; CHECK-NEXT: vsubuwm 3, 4, 3
[DAGCombiner] fold 'not' with signbit math This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
2018-07-28 00:42:55 +08:00
; CHECK-NEXT: vsraw 2, 2, 3
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
; CHECK-NEXT: lvx 3, 0, 3
[DAGCombiner] fold 'not' with signbit math This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
2018-07-28 00:42:55 +08:00
; CHECK-NEXT: vadduwm 2, 2, 3
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
; CHECK-NEXT: blr
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r
}
define i32 @sub_lshr_not(i32 %x) {
; CHECK-LABEL: sub_lshr_not:
; CHECK: # %bb.0:
; CHECK-NEXT: srwi 3, 3, 31
[DAGCombiner] fold 'not' with signbit math This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
2018-07-28 00:42:55 +08:00
; CHECK-NEXT: ori 3, 3, 42
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
; CHECK-NEXT: blr
%not = xor i32 %x, -1
%sh = lshr i32 %not, 31
%r = sub i32 43, %sh
ret i32 %r
}
define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: sub_lshr_not_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vsrw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3
[DAGCombiner] fold 'not' with signbit math This is a follow-up suggested in D48970. Alive proofs: https://rise4fun.com/Alive/sII We can eliminate an instruction in the usual select-of-constants to bit hack transform by adjusting the add/sub with constant. This is always a win. There are more transforms that are likely wins, but they may need target hooks in case some targets do not benefit. This is another step towards making up for canonicalizing to select-of-constants in rL331486. llvm-svn: 338132
2018-07-28 00:42:55 +08:00
; CHECK-NEXT: vadduwm 2, 2, 3
[PowerPC] add more tests for signbit math; NFC llvm-svn: 338130
2018-07-28 00:22:18 +08:00
; CHECK-NEXT: blr
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
ret <4 x i32> %r
}
[AArch64, PowerPC, x86] add more signbit math tests; NFC llvm-svn: 338143
2018-07-28 02:12:29 +08:00
define i32 @sub_lshr(i32 %x) {
; CHECK-LABEL: sub_lshr:
; CHECK: # %bb.0:
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 43
; CHECK-NEXT: blr
%sh = lshr i32 %x, 31
%r = sub i32 43, %sh
ret i32 %r
}
define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: sub_lshr_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI19_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI19_0@toc@l
; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vsrw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vsubuwm 2, 3, 2
; CHECK-NEXT: blr
%e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
ret <4 x i32> %r
}