maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll

49 lines
2.1 KiB
LLVM
Raw Normal View History

AMDGPU: Fix dropping mem operands when moving to VALU Without a memory operand, mayLoad or mayStore instructions are treated as hasUnorderedMemRef, which results in much worse scheduling. We really should have a verifier check that any non-side effecting mayLoad or mayStore has a memory operand. There are a few instructions (interp and images) which I'm not sure what / where to add these. llvm-svn: 246356
2015-08-29 14:48:46 +08:00
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; The memory operand was dropped from the buffer_load_dword_offset
; when replaced with the addr64 during operand legalization, resulting
; in the global loads not being scheduled together.
; GCN-LABEL: {{^}}reschedule_global_load_lds_store:
; GCN: buffer_load_dword
; GCN: buffer_load_dword
AMDGPU/SI: Enable load-store-opt by default. Summary: Enable load-store-opt by default, and update LIT tests. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D20694 llvm-svn: 270894
2016-05-27 03:35:29 +08:00
; GCN: ds_write2_b32
AMDGPU: Fix dropping mem operands when moving to VALU Without a memory operand, mayLoad or mayStore instructions are treated as hasUnorderedMemRef, which results in much worse scheduling. We really should have a verifier check that any non-side effecting mayLoad or mayStore has a memory operand. There are a few instructions (interp and images) which I'm not sure what / where to add these. llvm-svn: 246356
2015-08-29 14:48:46 +08:00
; GCN: s_endpgm
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @reschedule_global_load_lds_store(i32 addrspace(1)* noalias %gptr0, i32 addrspace(1)* noalias %gptr1, i32 addrspace(3)* noalias %lptr, i32 %c) #0 {
AMDGPU: Fix dropping mem operands when moving to VALU Without a memory operand, mayLoad or mayStore instructions are treated as hasUnorderedMemRef, which results in much worse scheduling. We really should have a verifier check that any non-side effecting mayLoad or mayStore has a memory operand. There are a few instructions (interp and images) which I'm not sure what / where to add these. llvm-svn: 246356
2015-08-29 14:48:46 +08:00
entry:
AMDGPU: Remove some old intrinsic uses from tests llvm-svn: 260493
2016-02-11 14:02:01 +08:00
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1
AMDGPU: Fix dropping mem operands when moving to VALU Without a memory operand, mayLoad or mayStore instructions are treated as hasUnorderedMemRef, which results in much worse scheduling. We really should have a verifier check that any non-side effecting mayLoad or mayStore has a memory operand. There are a few instructions (interp and images) which I'm not sure what / where to add these. llvm-svn: 246356
2015-08-29 14:48:46 +08:00
%idx = shl i32 %tid, 2
%gep0 = getelementptr i32, i32 addrspace(1)* %gptr0, i32 %idx
%gep1 = getelementptr i32, i32 addrspace(1)* %gptr1, i32 %idx
%gep2 = getelementptr i32, i32 addrspace(3)* %lptr, i32 %tid
%cmp0 = icmp eq i32 %c, 0
br i1 %cmp0, label %for.body, label %exit
for.body: ; preds = %for.body, %entry
%i = phi i32 [ 0, %entry ], [ %i.inc, %for.body ]
%gptr0.phi = phi i32 addrspace(1)* [ %gep0, %entry ], [ %gep0.inc, %for.body ]
%gptr1.phi = phi i32 addrspace(1)* [ %gep1, %entry ], [ %gep1.inc, %for.body ]
%lptr0.phi = phi i32 addrspace(3)* [ %gep2, %entry ], [ %gep2.inc, %for.body ]
AMDGPU: Make vectorization defeating test changes Simplifies test updates in the future. llvm-svn: 270736
2016-05-26 01:42:39 +08:00
%lptr1 = getelementptr i32, i32 addrspace(3)* %lptr0.phi, i32 2
AMDGPU: Fix dropping mem operands when moving to VALU Without a memory operand, mayLoad or mayStore instructions are treated as hasUnorderedMemRef, which results in much worse scheduling. We really should have a verifier check that any non-side effecting mayLoad or mayStore has a memory operand. There are a few instructions (interp and images) which I'm not sure what / where to add these. llvm-svn: 246356
2015-08-29 14:48:46 +08:00
%val0 = load i32, i32 addrspace(1)* %gep0
store i32 %val0, i32 addrspace(3)* %lptr0.phi
%val1 = load i32, i32 addrspace(1)* %gep1
store i32 %val1, i32 addrspace(3)* %lptr1
%gep0.inc = getelementptr i32, i32 addrspace(1)* %gptr0.phi, i32 4
%gep1.inc = getelementptr i32, i32 addrspace(1)* %gptr1.phi, i32 4
%gep2.inc = getelementptr i32, i32 addrspace(3)* %lptr0.phi, i32 4
%i.inc = add nsw i32 %i, 1
%cmp1 = icmp ne i32 %i, 256
br i1 %cmp1, label %for.body, label %exit
exit: ; preds = %for.body, %entry
ret void
}
; Function Attrs: nounwind readnone
AMDGPU: Remove some old intrinsic uses from tests llvm-svn: 260493
2016-02-11 14:02:01 +08:00
declare i32 @llvm.amdgcn.workitem.id.x() #1
AMDGPU: Fix dropping mem operands when moving to VALU Without a memory operand, mayLoad or mayStore instructions are treated as hasUnorderedMemRef, which results in much worse scheduling. We really should have a verifier check that any non-side effecting mayLoad or mayStore has a memory operand. There are a few instructions (interp and images) which I'm not sure what / where to add these. llvm-svn: 246356
2015-08-29 14:48:46 +08:00
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
AMDGPU: Switch barrier intrinsics to using convergent noduplicate prevents unrolling of small loops that happen to have barriers in them. If a loop has a barrier in it, it is OK to duplicate it for the unroll. llvm-svn: 256075
2015-12-19 09:46:41 +08:00
attributes #2 = { convergent nounwind }