forked from OSchip/llvm-project
35 lines
1.7 KiB
LLVM
35 lines
1.7 KiB
LLVM
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; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GCN,VI,PREGFX9 %s
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; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX81,PREGFX9 %s
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; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX9 %s
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; Testing for failures in divergence calculations when divergent intrinsic is lowered during instruction selection
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@0 = external dso_local addrspace(4) constant [4 x <4 x float>]
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; GCN-LABEL: {{^}}_amdgpu_ps_main:
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; GCN-NOT: v_readfirstlane
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; PRE-GFX9: flat_load_dword
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; GFX9: global_load
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define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %arg) local_unnamed_addr #0 {
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.entry:
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%tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %arg) #1
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%tmp1 = bitcast float %tmp to i32
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%tmp2 = srem i32 %tmp1, 4
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%tmp3 = select i1 false, i32 undef, i32 %tmp2
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%tmp4 = sext i32 %tmp3 to i64
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%tmp5 = getelementptr [4 x <4 x float>], [4 x <4 x float>] addrspace(4)* @0, i64 0, i64 %tmp4
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%tmp6 = load <4 x float>, <4 x float> addrspace(4)* %tmp5, align 16
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%tmp7 = extractelement <4 x float> %tmp6, i32 3
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%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7) #1
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x half> %tmp8, i1 true, i1 true) #2
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ret void
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}
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #2
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attributes #0 = { nounwind "InitialPSInputAddr"="0" }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind }
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