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llvm-project/llvm/test/CodeGen/AMDGPU/bswap.ll

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DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
declare i16 @llvm.bswap.i16(i16) nounwind readnone
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
declare i32 @llvm.bswap.i32(i32) nounwind readnone
declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
R600/SI: Add pattern for bswap llvm-svn: 220304
2014-10-22 00:25:08 +08:00
declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
declare i64 @llvm.bswap.i64(i64) nounwind readnone
declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
R600/SI: Add pattern for bswap llvm-svn: 220304
2014-10-22 00:25:08 +08:00
; FUNC-LABEL: @test_bswap_i32
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; GCN: s_load_dword [[VAL:s[0-9]+]]
; GCN-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8
; GCN-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff
; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
; GCN: buffer_store_dword [[RESULT]]
; GCN: s_endpgm
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load i32, i32 addrspace(1)* %in, align 4
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
%bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
store i32 %bswap, i32 addrspace(1)* %out, align 4
ret void
}
R600/SI: Add pattern for bswap llvm-svn: 220304
2014-10-22 00:25:08 +08:00
; FUNC-LABEL: @test_bswap_v2i32
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN: s_endpgm
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
ret void
}
R600/SI: Add pattern for bswap llvm-svn: 220304
2014-10-22 00:25:08 +08:00
; FUNC-LABEL: @test_bswap_v4i32
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN: s_endpgm
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
ret void
}
R600/SI: Add pattern for bswap llvm-svn: 220304
2014-10-22 00:25:08 +08:00
; FUNC-LABEL: @test_bswap_v8i32
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_alignbit_b32
; GCN-DAG: v_bfi_b32
; GCN: s_endpgm
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
R600/SI: Add pattern for bswap llvm-svn: 220304
2014-10-22 00:25:08 +08:00
%bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
ret void
}
AMDGPU: Improve splitting 64-bit bit ops by constants This addresses a TODO to handle operations besides and. This also starts eliminating no-op operations with a constant that can emerge later. llvm-svn: 281488
2016-09-14 23:19:03 +08:00
; FUNC-LABEL: {{^}}test_bswap_i64:
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; GCN-NOT: v_or_b32_e64 v{{[0-9]+}}, 0, 0
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load i64, i64 addrspace(1)* %in, align 8
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
%bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
store i64 %bswap, i64 addrspace(1)* %out, align 8
ret void
}
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
ret void
}
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
R600: Fix selection failure for vector bswap llvm-svn: 210475
2014-06-10 00:20:25 +08:00
%bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
ret void
}
DAG: Fix not truncating when promoting bswap/bitreverse These need to convert back to the original type, like any other promotion. llvm-svn: 323932
2018-02-01 07:54:16 +08:00
; GCN-LABEL: {{^}}missing_truncate_promote_bswap:
; VI: v_and_b32
; VI: v_alignbit_b32
; VI: v_alignbit_b32
; VI: v_bfi_b32
define float @missing_truncate_promote_bswap(i32 %arg) {
bb:
%tmp = trunc i32 %arg to i16
%tmp1 = call i16 @llvm.bswap.i16(i16 %tmp)
%tmp2 = bitcast i16 %tmp1 to half
%tmp3 = fpext half %tmp2 to float
ret float %tmp3
}