forked from OSchip/llvm-project
289 lines
14 KiB
LLVM
289 lines
14 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX908 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
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; GCN-LABEL: {{^}}max_10_vgprs:
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; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; GFX908-NOT: SCRATCH_RSRC
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; GFX908-DAG: v_accvgpr_write_b32 a0, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a1, v{{[0-9]}}
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; GFX900: buffer_store_dword v{{[0-9]}},
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; GFX900: buffer_store_dword v{{[0-9]}},
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; GFX900: buffer_load_dword v{{[0-9]}},
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; GFX900: buffer_load_dword v{{[0-9]}},
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; GFX908-NOT: buffer_
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; GFX908-DAG v_accvgpr_read_b32 v{{[0-9]}}, a0
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a1
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; GCN: NumVgprs: 10
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; GFX900: ScratchSize: 12
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; GFX908: ScratchSize: 0
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; GCN: VGPRBlocks: 2
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; GCN: NumVGPRsForWavesPerEU: 10
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define amdgpu_kernel void @max_10_vgprs(i32 addrspace(1)* %p) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%p1 = getelementptr inbounds i32, i32 addrspace(1)* %p, i32 %tid
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%p2 = getelementptr inbounds i32, i32 addrspace(1)* %p1, i32 4
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%p3 = getelementptr inbounds i32, i32 addrspace(1)* %p2, i32 8
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%p4 = getelementptr inbounds i32, i32 addrspace(1)* %p3, i32 12
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%p5 = getelementptr inbounds i32, i32 addrspace(1)* %p4, i32 16
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%p6 = getelementptr inbounds i32, i32 addrspace(1)* %p5, i32 20
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%p7 = getelementptr inbounds i32, i32 addrspace(1)* %p6, i32 24
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%p8 = getelementptr inbounds i32, i32 addrspace(1)* %p7, i32 28
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%p9 = getelementptr inbounds i32, i32 addrspace(1)* %p8, i32 32
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%p10 = getelementptr inbounds i32, i32 addrspace(1)* %p9, i32 36
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%v1 = load volatile i32, i32 addrspace(1)* %p1
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%v2 = load volatile i32, i32 addrspace(1)* %p2
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%v3 = load volatile i32, i32 addrspace(1)* %p3
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%v4 = load volatile i32, i32 addrspace(1)* %p4
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%v5 = load volatile i32, i32 addrspace(1)* %p5
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%v6 = load volatile i32, i32 addrspace(1)* %p6
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%v7 = load volatile i32, i32 addrspace(1)* %p7
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%v8 = load volatile i32, i32 addrspace(1)* %p8
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%v9 = load volatile i32, i32 addrspace(1)* %p9
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%v10 = load volatile i32, i32 addrspace(1)* %p10
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call void asm sideeffect "", "v,v,v,v,v,v,v,v,v,v"(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, i32 %v9, i32 %v10)
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store volatile i32 %v1, i32 addrspace(1)* undef
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store volatile i32 %v2, i32 addrspace(1)* undef
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store volatile i32 %v3, i32 addrspace(1)* undef
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store volatile i32 %v4, i32 addrspace(1)* undef
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store volatile i32 %v5, i32 addrspace(1)* undef
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store volatile i32 %v6, i32 addrspace(1)* undef
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store volatile i32 %v7, i32 addrspace(1)* undef
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store volatile i32 %v8, i32 addrspace(1)* undef
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store volatile i32 %v9, i32 addrspace(1)* undef
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store volatile i32 %v10, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}max_10_vgprs_used_9a:
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; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; GFX908: v_accvgpr_write_b32 a9, v{{[0-9]}}
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; GCN: buffer_store_dword v{{[0-9]}},
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; GFX900: buffer_store_dword v{{[0-9]}},
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; GFX900: buffer_load_dword v{{[0-9]}},
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; GFX900: buffer_load_dword v{{[0-9]}},
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; GFX908-NOT: buffer_
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; GFX908: v_accvgpr_read_b32 v{{[0-9]}}, a9
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; GFX908: buffer_load_dword v{{[0-9]}},
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; GFX908-NOT: buffer_
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; GCN: NumVgprs: 10
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; GFX900: ScratchSize: 12
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; GFX908: ScratchSize: 8
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; GCN: VGPRBlocks: 2
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; GCN: NumVGPRsForWavesPerEU: 10
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define amdgpu_kernel void @max_10_vgprs_used_9a(i32 addrspace(1)* %p) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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call void asm sideeffect "", "a,a,a,a,a,a,a,a,a"(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9)
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%p1 = getelementptr inbounds i32, i32 addrspace(1)* %p, i32 %tid
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%p2 = getelementptr inbounds i32, i32 addrspace(1)* %p1, i32 4
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%p3 = getelementptr inbounds i32, i32 addrspace(1)* %p2, i32 8
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%p4 = getelementptr inbounds i32, i32 addrspace(1)* %p3, i32 12
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%p5 = getelementptr inbounds i32, i32 addrspace(1)* %p4, i32 16
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%p6 = getelementptr inbounds i32, i32 addrspace(1)* %p5, i32 20
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%p7 = getelementptr inbounds i32, i32 addrspace(1)* %p6, i32 24
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%p8 = getelementptr inbounds i32, i32 addrspace(1)* %p7, i32 28
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%p9 = getelementptr inbounds i32, i32 addrspace(1)* %p8, i32 32
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%p10 = getelementptr inbounds i32, i32 addrspace(1)* %p9, i32 36
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%v1 = load volatile i32, i32 addrspace(1)* %p1
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%v2 = load volatile i32, i32 addrspace(1)* %p2
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%v3 = load volatile i32, i32 addrspace(1)* %p3
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%v4 = load volatile i32, i32 addrspace(1)* %p4
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%v5 = load volatile i32, i32 addrspace(1)* %p5
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%v6 = load volatile i32, i32 addrspace(1)* %p6
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%v7 = load volatile i32, i32 addrspace(1)* %p7
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%v8 = load volatile i32, i32 addrspace(1)* %p8
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%v9 = load volatile i32, i32 addrspace(1)* %p9
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%v10 = load volatile i32, i32 addrspace(1)* %p10
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call void asm sideeffect "", "v,v,v,v,v,v,v,v,v,v"(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, i32 %v9, i32 %v10)
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store volatile i32 %v1, i32 addrspace(1)* undef
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store volatile i32 %v2, i32 addrspace(1)* undef
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store volatile i32 %v3, i32 addrspace(1)* undef
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store volatile i32 %v4, i32 addrspace(1)* undef
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store volatile i32 %v5, i32 addrspace(1)* undef
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store volatile i32 %v6, i32 addrspace(1)* undef
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store volatile i32 %v7, i32 addrspace(1)* undef
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store volatile i32 %v8, i32 addrspace(1)* undef
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store volatile i32 %v9, i32 addrspace(1)* undef
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store volatile i32 %v10, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}max_10_vgprs_used_1a_partial_spill:
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; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; GFX908-DAG: v_accvgpr_write_b32 a0, 1
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; GFX908-DAG: v_accvgpr_write_b32 a1, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a2, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a3, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a4, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a5, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a6, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a7, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a8, v{{[0-9]}}
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; GFX908-DAG: v_accvgpr_write_b32 a9, v{{[0-9]}}
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; GFX900: buffer_store_dword v{{[0-9]}},
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; GCN-DAG: buffer_store_dword v{{[0-9]}},
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; GFX900: buffer_load_dword v{{[0-9]}},
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; GCN-DAG: buffer_load_dword v{{[0-9]}},
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; GFX908-DAG v_accvgpr_read_b32 v{{[0-9]}}, a1
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a2
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a3
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a4
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a5
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a6
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a7
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a8
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; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a9
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; GCN: NumVgprs: 10
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; GFX900: ScratchSize: 44
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; GFX908: ScratchSize: 20
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; GCN: VGPRBlocks: 2
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; GCN: NumVGPRsForWavesPerEU: 10
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define amdgpu_kernel void @max_10_vgprs_used_1a_partial_spill(i64 addrspace(1)* %p) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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call void asm sideeffect "", "a"(i32 1)
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%p1 = getelementptr inbounds i64, i64 addrspace(1)* %p, i32 %tid
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%p2 = getelementptr inbounds i64, i64 addrspace(1)* %p1, i32 8
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%p3 = getelementptr inbounds i64, i64 addrspace(1)* %p2, i32 16
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%p4 = getelementptr inbounds i64, i64 addrspace(1)* %p3, i32 24
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%p5 = getelementptr inbounds i64, i64 addrspace(1)* %p4, i32 32
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%v1 = load volatile i64, i64 addrspace(1)* %p1
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%v2 = load volatile i64, i64 addrspace(1)* %p2
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%v3 = load volatile i64, i64 addrspace(1)* %p3
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%v4 = load volatile i64, i64 addrspace(1)* %p4
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%v5 = load volatile i64, i64 addrspace(1)* %p5
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call void asm sideeffect "", "v,v,v,v,v"(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5)
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store volatile i64 %v1, i64 addrspace(1)* %p2
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store volatile i64 %v2, i64 addrspace(1)* %p3
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store volatile i64 %v3, i64 addrspace(1)* %p4
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store volatile i64 %v4, i64 addrspace(1)* %p5
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store volatile i64 %v5, i64 addrspace(1)* %p1
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ret void
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}
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; GCN-LABEL: {{^}}max_10_vgprs_spill_v32:
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; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; GFX908-DAG: v_accvgpr_write_b32 a0,
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; GFX908-DAG: v_accvgpr_write_b32 a9, v{{[0-9]}}
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; GCN-NOT: a10
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; GCN: buffer_store_dword v{{[0-9]}},
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; GFX908: NumVgprs: 10
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; GFX900: ScratchSize: 100
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; GFX908: ScratchSize: 68
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; GFX908: VGPRBlocks: 2
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; GFX908: NumVGPRsForWavesPerEU: 10
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define amdgpu_kernel void @max_10_vgprs_spill_v32(<32 x float> addrspace(1)* %p) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p, i32 %tid
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%v = load volatile <32 x float>, <32 x float> addrspace(1)* %gep
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store volatile <32 x float> %v, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}max_256_vgprs_spill_9x32:
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; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; GFX908-NOT: SCRATCH_RSRC
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; GFX908-DAG: v_accvgpr_write_b32 a0, v
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; GFX900: buffer_store_dword v
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; GFX900: buffer_load_dword v
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; GFX908-NOT: buffer_
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; GFX908-DAG v_accvgpr_read_b32
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; GCN: NumVgprs: 256
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; GFX900: ScratchSize: 148
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; GFX908: ScratchSize: 0
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; GCN: VGPRBlocks: 63
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; GCN: NumVGPRsForWavesPerEU: 256
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define amdgpu_kernel void @max_256_vgprs_spill_9x32(<32 x float> addrspace(1)* %p) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%p1 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p, i32 %tid
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%p2 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p1, i32 %tid
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%p3 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p2, i32 %tid
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%p4 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p3, i32 %tid
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%p5 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p4, i32 %tid
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%p6 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p5, i32 %tid
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%p7 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p6, i32 %tid
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%p8 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p7, i32 %tid
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%p9 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p8, i32 %tid
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%v1 = load volatile <32 x float>, <32 x float> addrspace(1)* %p1
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%v2 = load volatile <32 x float>, <32 x float> addrspace(1)* %p2
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%v3 = load volatile <32 x float>, <32 x float> addrspace(1)* %p3
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%v4 = load volatile <32 x float>, <32 x float> addrspace(1)* %p4
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%v5 = load volatile <32 x float>, <32 x float> addrspace(1)* %p5
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%v6 = load volatile <32 x float>, <32 x float> addrspace(1)* %p6
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%v7 = load volatile <32 x float>, <32 x float> addrspace(1)* %p7
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%v8 = load volatile <32 x float>, <32 x float> addrspace(1)* %p8
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%v9 = load volatile <32 x float>, <32 x float> addrspace(1)* %p9
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store volatile <32 x float> %v1, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v2, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v3, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v4, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v5, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v6, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v7, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v8, <32 x float> addrspace(1)* undef
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store volatile <32 x float> %v9, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}max_256_vgprs_spill_9x32_2bb:
|
||
|
|
; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
|
||
|
|
; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
|
||
|
|
; GFX908-NOT: SCRATCH_RSRC
|
||
|
|
; GFX908-DAG: v_accvgpr_write_b32 a0, v
|
||
|
|
; GFX900: buffer_store_dword v
|
||
|
|
; GFX900: buffer_load_dword v
|
||
|
|
; GFX908-NOT: buffer_
|
||
|
|
; GFX908-DAG v_accvgpr_read_b32
|
||
|
|
|
||
|
|
; GCN: NumVgprs: 256
|
||
|
|
; GFX900: ScratchSize: 580
|
||
|
|
; GFX908: ScratchSize: 0
|
||
|
|
; GCN: VGPRBlocks: 63
|
||
|
|
; GCN: NumVGPRsForWavesPerEU: 256
|
||
|
|
define amdgpu_kernel void @max_256_vgprs_spill_9x32_2bb(<32 x float> addrspace(1)* %p) {
|
||
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||
|
|
%p1 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p, i32 %tid
|
||
|
|
%p2 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p1, i32 %tid
|
||
|
|
%p3 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p2, i32 %tid
|
||
|
|
%p4 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p3, i32 %tid
|
||
|
|
%p5 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p4, i32 %tid
|
||
|
|
%p6 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p5, i32 %tid
|
||
|
|
%p7 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p6, i32 %tid
|
||
|
|
%p8 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p7, i32 %tid
|
||
|
|
%p9 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p8, i32 %tid
|
||
|
|
%v1 = load volatile <32 x float>, <32 x float> addrspace(1)* %p1
|
||
|
|
%v2 = load volatile <32 x float>, <32 x float> addrspace(1)* %p2
|
||
|
|
%v3 = load volatile <32 x float>, <32 x float> addrspace(1)* %p3
|
||
|
|
%v4 = load volatile <32 x float>, <32 x float> addrspace(1)* %p4
|
||
|
|
%v5 = load volatile <32 x float>, <32 x float> addrspace(1)* %p5
|
||
|
|
%v6 = load volatile <32 x float>, <32 x float> addrspace(1)* %p6
|
||
|
|
%v7 = load volatile <32 x float>, <32 x float> addrspace(1)* %p7
|
||
|
|
%v8 = load volatile <32 x float>, <32 x float> addrspace(1)* %p8
|
||
|
|
%v9 = load volatile <32 x float>, <32 x float> addrspace(1)* %p9
|
||
|
|
br label %st
|
||
|
|
|
||
|
|
st:
|
||
|
|
store volatile <32 x float> %v1, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v2, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v3, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v4, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v5, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v6, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v7, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v8, <32 x float> addrspace(1)* undef
|
||
|
|
store volatile <32 x float> %v9, <32 x float> addrspace(1)* undef
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
declare i32 @llvm.amdgcn.workitem.id.x()
|
||
|
|
|
||
|
|
attributes #0 = { nounwind "amdgpu-num-vgpr"="10" }
|