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llvm-project/llvm/test/MC/AMDGPU/vop3-errs.s

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R600/SI: Improve AsmParser support for forced e64 encoding We can now force e64 encoding even when the operands would be legal for e32 encoding. llvm-svn: 235626
2015-04-24 03:33:48 +08:00
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s
v_add_f32_e64 v0, v1
// CHECK: error: too few operands for instruction
[AMDGPU][llvm-mc] Support for 32-bit inline literals Patch by: Artem Tamazov Summary: Note: Support for 64-bit inline literals TBD Added: Support of abs/neg modifiers for literals (incomplete; parsing TBD). Added: Some TODO comments. Reworked/clarity: rename isInlineImm() to isInlinableImm() Reworked/robustness: disallow BitsToFloat() with undefined value in isInlinableImm() Reworked/reuse: isSSrc32/64(), isVSrc32/64() Tests added. Reviewers: tstellarAMD, arsenm Subscribers: vpykhtin, nhaustov, SamWot, arsenm Projects: #llvm-amdgpu-spb Differential Revision: http://reviews.llvm.org/D17204 llvm-svn: 261559
2016-02-23 03:17:56 +08:00
v_div_scale_f32 v24, vcc, v22, 1.1, v22
// CHECK: error: invalid operand for instruction