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llvm-project/llvm/test/CodeGen/XCore/addsub64.ll

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Convert test to FileCheck. llvm-svn: 98148
2010-03-10 19:24:03 +08:00
; RUN: llc < %s -march=xcore | FileCheck %s
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand these operations if ladd/lsub are not available on the current subtarget. llvm-svn: 59305
2008-11-14 23:59:19 +08:00
define i64 @add64(i64 %a, i64 %b) {
%result = add i64 %a, %b
ret i64 %result
}
Convert test to FileCheck. llvm-svn: 98148
2010-03-10 19:24:03 +08:00
; CHECK: add64
; CHECK: ldc r11, 0
; CHECK-NEXT: ladd r2, r0, r0, r2, r11
; CHECK-NEXT: ladd r2, r1, r1, r3, r2
; CHECK-NEXT: retsp 0
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand these operations if ladd/lsub are not available on the current subtarget. llvm-svn: 59305
2008-11-14 23:59:19 +08:00
define i64 @sub64(i64 %a, i64 %b) {
%result = sub i64 %a, %b
ret i64 %result
}
Convert test to FileCheck. llvm-svn: 98148
2010-03-10 19:24:03 +08:00
; CHECK: sub64
; CHECK: ldc r11, 0
; CHECK-NEXT: lsub r2, r0, r0, r2, r11
; CHECK-NEXT: lsub r2, r1, r1, r3, r2
; CHECK-NEXT: retsp 0
Lower add (mul a, b), c into MACCU / MACCS nodes which translate directly to the maccu / maccs instructions. We handle this in ExpandADDSUB since after type legalisation it is messy to recognise these operations. llvm-svn: 98150
2010-03-10 19:41:08 +08:00
define i64 @maccu(i64 %a, i32 %b, i32 %c) {
entry:
%0 = zext i32 %b to i64
%1 = zext i32 %c to i64
%2 = mul i64 %1, %0
%3 = add i64 %2, %a
ret i64 %3
}
; CHECK: maccu:
; CHECK: maccu r1, r0, r3, r2
; CHECK-NEXT: retsp 0
define i64 @maccs(i64 %a, i32 %b, i32 %c) {
entry:
%0 = sext i32 %b to i64
%1 = sext i32 %c to i64
%2 = mul i64 %1, %0
%3 = add i64 %2, %a
ret i64 %3
}
; CHECK: maccs:
; CHECK: maccs r1, r0, r3, r2
; CHECK-NEXT: retsp 0
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all operands are zero extended. llvm-svn: 98168
2010-03-11 02:12:27 +08:00
define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
%0 = zext i32 %a to i64
%1 = zext i32 %b to i64
%2 = zext i32 %c to i64
%3 = zext i32 %d to i64
%4 = mul i64 %1, %0
%5 = add i64 %4, %2
%6 = add i64 %5, %3
ret i64 %6
}
; CHECK: lmul:
; CHECK: lmul r1, r0, r1, r0, r2, r3
; CHECK-NEXT: retsp 0