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llvm-project/llvm/test/MC/Mips/mips-fpu-instructions.s

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[mips] Correct the definition of cvt.d.w An upcoming patch D41434, changes the ordering of the matcher table for assembly. This patch corrects the definition of the normal MIPS cvt.d.w not to be available in microMIPS. llvm-svn: 325589
2018-02-20 23:55:17 +08:00
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -show-inst -mcpu=mips32r2 | FileCheck %s --check-prefixes=CHECK,CHECK-32
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -show-inst -mcpu=mips64r2 | FileCheck %s --check-prefixes=CHECK,CHECK-64
The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363
2012-09-07 08:23:42 +08:00
# Check that the assembler can handle the documented syntax
# for FPU instructions.
#------------------------------------------------------------------------------
# FP aritmetic instructions
#------------------------------------------------------------------------------
# CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
# CHECK: abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46]
# CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
# CHECK: add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46]
# CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
# CHECK: floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46]
# CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
# CHECK: ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46]
# CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
# CHECK: mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46]
# CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
# CHECK: neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46]
# CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
# CHECK: round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46]
# CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
# CHECK: sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46]
# CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
# CHECK: sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46]
# CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
# CHECK: trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46]
abs.d $f12,$f14
abs.s $f6,$f7
add.d $f8,$f12,$f14
add.s $f9,$f6,$f7
floor.w.d $f12,$f14
floor.w.s $f6,$f7
ceil.w.d $f12,$f14
ceil.w.s $f6,$f7
mul.d $f8,$f12,$f14
mul.s $f9,$f6, $f7
neg.d $f12,$f14
neg.s $f6,$f7
round.w.d $f12,$f14
round.w.s $f6,$f7
sqrt.d $f12,$f14
sqrt.s $f6,$f7
sub.d $f8,$f12,$f14
sub.s $f9,$f6,$f7
trunc.w.d $f12,$f14
trunc.w.s $f6,$f7
#------------------------------------------------------------------------------
# FP compare instructions
#------------------------------------------------------------------------------
# CHECK: c.eq.d $f12, $f14 # encoding: [0x32,0x60,0x2e,0x46]
# CHECK: c.eq.s $f6, $f7 # encoding: [0x32,0x30,0x07,0x46]
# CHECK: c.f.d $f12, $f14 # encoding: [0x30,0x60,0x2e,0x46]
# CHECK: c.f.s $f6, $f7 # encoding: [0x30,0x30,0x07,0x46]
# CHECK: c.le.d $f12, $f14 # encoding: [0x3e,0x60,0x2e,0x46]
# CHECK: c.le.s $f6, $f7 # encoding: [0x3e,0x30,0x07,0x46]
# CHECK: c.lt.d $f12, $f14 # encoding: [0x3c,0x60,0x2e,0x46]
# CHECK: c.lt.s $f6, $f7 # encoding: [0x3c,0x30,0x07,0x46]
# CHECK: c.nge.d $f12, $f14 # encoding: [0x3d,0x60,0x2e,0x46]
# CHECK: c.nge.s $f6, $f7 # encoding: [0x3d,0x30,0x07,0x46]
# CHECK: c.ngl.d $f12, $f14 # encoding: [0x3b,0x60,0x2e,0x46]
# CHECK: c.ngl.s $f6, $f7 # encoding: [0x3b,0x30,0x07,0x46]
# CHECK: c.ngle.d $f12, $f14 # encoding: [0x39,0x60,0x2e,0x46]
# CHECK: c.ngle.s $f6, $f7 # encoding: [0x39,0x30,0x07,0x46]
# CHECK: c.ngt.d $f12, $f14 # encoding: [0x3f,0x60,0x2e,0x46]
# CHECK: c.ngt.s $f6, $f7 # encoding: [0x3f,0x30,0x07,0x46]
# CHECK: c.ole.d $f12, $f14 # encoding: [0x36,0x60,0x2e,0x46]
# CHECK: c.ole.s $f6, $f7 # encoding: [0x36,0x30,0x07,0x46]
# CHECK: c.olt.d $f12, $f14 # encoding: [0x34,0x60,0x2e,0x46]
# CHECK: c.olt.s $f6, $f7 # encoding: [0x34,0x30,0x07,0x46]
# CHECK: c.seq.d $f12, $f14 # encoding: [0x3a,0x60,0x2e,0x46]
# CHECK: c.seq.s $f6, $f7 # encoding: [0x3a,0x30,0x07,0x46]
# CHECK: c.sf.d $f12, $f14 # encoding: [0x38,0x60,0x2e,0x46]
# CHECK: c.sf.s $f6, $f7 # encoding: [0x38,0x30,0x07,0x46]
# CHECK: c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46]
# CHECK: c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46]
# CHECK: c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46]
# CHECK: c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46]
# CHECK: c.ult.d $f12, $f14 # encoding: [0x35,0x60,0x2e,0x46]
# CHECK: c.ult.s $f6, $f7 # encoding: [0x35,0x30,0x07,0x46]
# CHECK: c.un.d $f12, $f14 # encoding: [0x31,0x60,0x2e,0x46]
# CHECK: c.un.s $f6, $f7 # encoding: [0x31,0x30,0x07,0x46]
c.eq.d $f12,$f14
c.eq.s $f6,$f7
c.f.d $f12,$f14
c.f.s $f6,$f7
c.le.d $f12,$f14
c.le.s $f6,$f7
c.lt.d $f12,$f14
c.lt.s $f6,$f7
c.nge.d $f12,$f14
c.nge.s $f6,$f7
c.ngl.d $f12,$f14
c.ngl.s $f6,$f7
c.ngle.d $f12,$f14
c.ngle.s $f6,$f7
c.ngt.d $f12,$f14
c.ngt.s $f6,$f7
c.ole.d $f12,$f14
c.ole.s $f6,$f7
c.olt.d $f12,$f14
c.olt.s $f6,$f7
c.seq.d $f12,$f14
c.seq.s $f6,$f7
c.sf.d $f12,$f14
c.sf.s $f6,$f7
c.ueq.d $f12,$f14
c.ueq.s $f28,$f18
c.ule.d $f12,$f14
c.ule.s $f6,$f7
c.ult.d $f12,$f14
c.ult.s $f6,$f7
c.un.d $f12,$f14
c.un.s $f6,$f7
#------------------------------------------------------------------------------
# FP convert instructions
#------------------------------------------------------------------------------
# CHECK: cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46]
# CHECK: cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46]
[mips] Correct the definition of cvt.d.w An upcoming patch D41434, changes the ordering of the matcher table for assembly. This patch corrects the definition of the normal MIPS cvt.d.w not to be available in microMIPS. llvm-svn: 325589
2018-02-20 23:55:17 +08:00
# CHECK-32: # <MCInst #{{.*}} CVT_D32_W
# CHECK-64: # <MCInst #{{.*}} CVT_D64_W
The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363
2012-09-07 08:23:42 +08:00
# CHECK: cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46]
# CHECK: cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46]
# CHECK: cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46]
# CHECK: cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46]
cvt.d.s $f6,$f7
cvt.d.w $f12,$f14
cvt.s.d $f12,$f14
cvt.s.w $f6,$f7
cvt.w.d $f12,$f14
cvt.w.s $f6,$f7
#------------------------------------------------------------------------------
# FP move instructions
#------------------------------------------------------------------------------
This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand. llvm-svn: 194562
2013-11-13 17:48:53 +08:00
# CHECK: bc1f $BB_1 # encoding: [A,A,0x00,0x45]
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK: # fixup A - offset: 0, value: ($BB_1)-4, kind: fixup_Mips_PC16
The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363
2012-09-07 08:23:42 +08:00
[mips] Fix MipsAsmParser::parseCCRRegs. Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861
2013-07-23 03:30:38 +08:00
# CHECK: cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44]
# CHECK: ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44]
The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363
2012-09-07 08:23:42 +08:00
# CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44]
# CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00]
# CHECK: mflo $5 # encoding: [0x12,0x28,0x00,0x00]
# CHECK: mov.d $f6, $f8 # encoding: [0x86,0x41,0x20,0x46]
# CHECK: mov.s $f6, $f7 # encoding: [0x86,0x39,0x00,0x46]
# CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
# CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00]
# CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00]
# CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
Adding support for instructions mfc0, mfc2, mtc0, mtc2 move from and to coprocessors 0 and 2. Contributer: Vladimir Medic llvm-svn: 165351
2012-10-06 09:17:37 +08:00
# CHECK: mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40]
# CHECK: mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40]
# CHECK: mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48]
# CHECK: mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48]
# CHECK: mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40]
# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48]
# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
Mips assembler: Explicit floating point condition register recognition. This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic llvm-svn: 179567
2013-04-16 06:21:55 +08:00
# CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
# CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00]
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
# CHECK: movt $4, $5, $fcc4 # encoding: [0x01,0x20,0xb1,0x00]
# CHECK: movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46]
# CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch. llvm-svn: 186567
2013-07-18 17:28:35 +08:00
# CHECK: luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c]
# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c]
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
# CHECK: lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d]
# CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e]
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit. llvm-svn: 190397
2013-09-10 17:50:01 +08:00
# CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
# CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added. llvm-svn: 190780
2013-09-16 18:29:42 +08:00
# CHECK: swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb]
# CHECK: sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb]
# CHECK: lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb]
# CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]
This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand. llvm-svn: 194562
2013-11-13 17:48:53 +08:00
bc1f $fcc0, $BB_1
The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363
2012-09-07 08:23:42 +08:00
cfc1 $a2,$0
[mips] Fix MipsAsmParser::parseCCRRegs. Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861
2013-07-23 03:30:38 +08:00
ctc1 $10,$31
The Mips standalone assembler fpu instruction support. Test cases included Contributer: Vladimir Medic llvm-svn: 163363
2012-09-07 08:23:42 +08:00
mfc1 $a2,$f7
mfhi $a1
mflo $a1
mov.d $f6,$f8
mov.s $f6,$f7
mtc1 $a2,$f7
mthi $a3
mtlo $a3
swc1 $f9,9158($a3)
Adding support for instructions mfc0, mfc2, mtc0, mtc2 move from and to coprocessors 0 and 2. Contributer: Vladimir Medic llvm-svn: 165351
2012-10-06 09:17:37 +08:00
mfc0 $6, $7
mtc0 $9, $8
mfc2 $5, $7
mtc2 $9, $4
mfc0 $6, $7, 2
mtc0 $9, $8, 3
mfc2 $5, $7, 4
mtc2 $9, $4, 5
Mips assembler: Explicit floating point condition register recognition. This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic llvm-svn: 179567
2013-04-16 06:21:55 +08:00
movf $2, $1, $fcc0
movt $2, $1, $fcc0
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
movt $4, $5, $fcc4
movf.d $f4, $f6, $fcc2
movf.s $f4, $f6, $fcc5
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
luxc1 $f0, $a2($a1)
suxc1 $f4, $t8($a1)
lwxc1 $f20, $12($14)
swxc1 $f26, $s2($s6)
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit. llvm-svn: 190397
2013-09-10 17:50:01 +08:00
mfhc1 $17, $f4
mthc1 $17, $f6
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added. llvm-svn: 190780
2013-09-16 18:29:42 +08:00
swc2 $4, 16($sp)
sdc2 $4, 16($sp)
lwc2 $11, 12($ra)
ldc2 $11, 12($ra)