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llvm-project/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt

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Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
# CHECK: lfs 2, 128(4)
0xc0 0x44 0x00 0x80
# CHECK: lfsx 2, 3, 4
0x7c 0x43 0x24 0x2e
# CHECK: lfsu 2, 128(4)
0xc4 0x44 0x00 0x80
# CHECK: lfsux 2, 3, 4
0x7c 0x43 0x24 0x6e
# CHECK: lfd 2, 128(4)
0xc8 0x44 0x00 0x80
# CHECK: lfdx 2, 3, 4
0x7c 0x43 0x24 0xae
# CHECK: lfdu 2, 128(4)
0xcc 0x44 0x00 0x80
# CHECK: lfdux 2, 3, 4
0x7c 0x43 0x24 0xee
# CHECK: lfiwax 2, 3, 4
0x7c 0x43 0x26 0xae
# CHECK: lfiwzx 2, 3, 4
0x7c 0x43 0x26 0xee
# CHECK: stfs 2, 128(4)
0xd0 0x44 0x00 0x80
# CHECK: stfsx 2, 3, 4
0x7c 0x43 0x25 0x2e
# CHECK: stfsu 2, 128(4)
0xd4 0x44 0x00 0x80
# CHECK: stfsux 2, 3, 4
0x7c 0x43 0x25 0x6e
# CHECK: stfd 2, 128(4)
0xd8 0x44 0x00 0x80
# CHECK: stfdx 2, 3, 4
0x7c 0x43 0x25 0xae
# CHECK: stfdu 2, 128(4)
0xdc 0x44 0x00 0x80
# CHECK: stfdux 2, 3, 4
0x7c 0x43 0x25 0xee
# CHECK: stfiwx 2, 3, 4
0x7c 0x43 0x27 0xae
# CHECK: fmr 2, 3
0xfc 0x40 0x18 0x90
# CHECK: fmr. 2, 3
0xfc 0x40 0x18 0x91
# CHECK: fneg 2, 3
0xfc 0x40 0x18 0x50
# CHECK: fneg. 2, 3
0xfc 0x40 0x18 0x51
# CHECK: fabs 2, 3
0xfc 0x40 0x1a 0x10
# CHECK: fabs. 2, 3
0xfc 0x40 0x1a 0x11
# CHECK: fnabs 2, 3
0xfc 0x40 0x19 0x10
# CHECK: fnabs. 2, 3
0xfc 0x40 0x19 0x11
# CHECK: fcpsgn 2, 3, 4
0xfc 0x43 0x20 0x10
# CHECK: fcpsgn. 2, 3, 4
0xfc 0x43 0x20 0x11
# CHECK: fadd 2, 3, 4
0xfc 0x43 0x20 0x2a
# CHECK: fadd. 2, 3, 4
0xfc 0x43 0x20 0x2b
# CHECK: fadds 2, 3, 4
0xec 0x43 0x20 0x2a
# CHECK: fadds. 2, 3, 4
0xec 0x43 0x20 0x2b
# CHECK: fsub 2, 3, 4
0xfc 0x43 0x20 0x28
# CHECK: fsub. 2, 3, 4
0xfc 0x43 0x20 0x29
# CHECK: fsubs 2, 3, 4
0xec 0x43 0x20 0x28
# CHECK: fsubs. 2, 3, 4
0xec 0x43 0x20 0x29
# CHECK: fmul 2, 3, 4
0xfc 0x43 0x01 0x32
# CHECK: fmul. 2, 3, 4
0xfc 0x43 0x01 0x33
# CHECK: fmuls 2, 3, 4
0xec 0x43 0x01 0x32
# CHECK: fmuls. 2, 3, 4
0xec 0x43 0x01 0x33
# CHECK: fdiv 2, 3, 4
0xfc 0x43 0x20 0x24
# CHECK: fdiv. 2, 3, 4
0xfc 0x43 0x20 0x25
# CHECK: fdivs 2, 3, 4
0xec 0x43 0x20 0x24
# CHECK: fdivs. 2, 3, 4
0xec 0x43 0x20 0x25
# CHECK: fsqrt 2, 3
0xfc 0x40 0x18 0x2c
# CHECK: fsqrt. 2, 3
0xfc 0x40 0x18 0x2d
# CHECK: fsqrts 2, 3
0xec 0x40 0x18 0x2c
# CHECK: fsqrts. 2, 3
0xec 0x40 0x18 0x2d
# CHECK: fre 2, 3
0xfc 0x40 0x18 0x30
# CHECK: fre. 2, 3
0xfc 0x40 0x18 0x31
# CHECK: fres 2, 3
0xec 0x40 0x18 0x30
# CHECK: fres. 2, 3
0xec 0x40 0x18 0x31
# CHECK: frsqrte 2, 3
0xfc 0x40 0x18 0x34
# CHECK: frsqrte. 2, 3
0xfc 0x40 0x18 0x35
# CHECK: frsqrtes 2, 3
0xec 0x40 0x18 0x34
# CHECK: frsqrtes. 2, 3
0xec 0x40 0x18 0x35
# CHECK: fmadd 2, 3, 4, 5
0xfc 0x43 0x29 0x3a
# CHECK: fmadd. 2, 3, 4, 5
0xfc 0x43 0x29 0x3b
# CHECK: fmadds 2, 3, 4, 5
0xec 0x43 0x29 0x3a
# CHECK: fmadds. 2, 3, 4, 5
0xec 0x43 0x29 0x3b
# CHECK: fmsub 2, 3, 4, 5
0xfc 0x43 0x29 0x38
# CHECK: fmsub. 2, 3, 4, 5
0xfc 0x43 0x29 0x39
# CHECK: fmsubs 2, 3, 4, 5
0xec 0x43 0x29 0x38
# CHECK: fmsubs. 2, 3, 4, 5
0xec 0x43 0x29 0x39
# CHECK: fnmadd 2, 3, 4, 5
0xfc 0x43 0x29 0x3e
# CHECK: fnmadd. 2, 3, 4, 5
0xfc 0x43 0x29 0x3f
# CHECK: fnmadds 2, 3, 4, 5
0xec 0x43 0x29 0x3e
# CHECK: fnmadds. 2, 3, 4, 5
0xec 0x43 0x29 0x3f
# CHECK: fnmsub 2, 3, 4, 5
0xfc 0x43 0x29 0x3c
# CHECK: fnmsub. 2, 3, 4, 5
0xfc 0x43 0x29 0x3d
# CHECK: fnmsubs 2, 3, 4, 5
0xec 0x43 0x29 0x3c
# CHECK: fnmsubs. 2, 3, 4, 5
0xec 0x43 0x29 0x3d
# CHECK: frsp 2, 3
0xfc 0x40 0x18 0x18
# CHECK: frsp. 2, 3
0xfc 0x40 0x18 0x19
# CHECK: fctid 2, 3
0xfc 0x40 0x1e 0x5c
# CHECK: fctid. 2, 3
0xfc 0x40 0x1e 0x5d
[PowerPC] Implement missing ISA 2.06 instructions. Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement them and add corresponding test cases in this patch. llvm-svn: 291116
2017-01-05 23:00:45 +08:00
# CHECK: fctidu 2, 3
0xfc 0x40 0x1f 0x5c
# CHECK: fctidu. 2, 3
0xfc 0x40 0x1f 0x5d
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# CHECK: fctidz 2, 3
0xfc 0x40 0x1e 0x5e
# CHECK: fctidz. 2, 3
0xfc 0x40 0x1e 0x5f
# CHECK: fctiduz 2, 3
0xfc 0x40 0x1f 0x5e
# CHECK: fctiduz. 2, 3
0xfc 0x40 0x1f 0x5f
# CHECK: fctiw 2, 3
0xfc 0x40 0x18 0x1c
# CHECK: fctiw. 2, 3
0xfc 0x40 0x18 0x1d
[PowerPC] Implement missing ISA 2.06 instructions. Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement them and add corresponding test cases in this patch. llvm-svn: 291116
2017-01-05 23:00:45 +08:00
# CHECK: fctiwu 2, 3
0xfc 0x40 0x19 0x1c
# CHECK: fctiwu. 2, 3
0xfc 0x40 0x19 0x1d
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# CHECK: fctiwz 2, 3
0xfc 0x40 0x18 0x1e
# CHECK: fctiwz. 2, 3
0xfc 0x40 0x18 0x1f
# CHECK: fctiwuz 2, 3
0xfc 0x40 0x19 0x1e
# CHECK: fctiwuz. 2, 3
0xfc 0x40 0x19 0x1f
# CHECK: fcfid 2, 3
0xfc 0x40 0x1e 0x9c
# CHECK: fcfid. 2, 3
0xfc 0x40 0x1e 0x9d
# CHECK: fcfidu 2, 3
0xfc 0x40 0x1f 0x9c
# CHECK: fcfidu. 2, 3
0xfc 0x40 0x1f 0x9d
# CHECK: fcfids 2, 3
0xec 0x40 0x1e 0x9c
# CHECK: fcfids. 2, 3
0xec 0x40 0x1e 0x9d
# CHECK: fcfidus 2, 3
0xec 0x40 0x1f 0x9c
# CHECK: fcfidus. 2, 3
0xec 0x40 0x1f 0x9d
# CHECK: frin 2, 3
0xfc 0x40 0x1b 0x10
# CHECK: frin. 2, 3
0xfc 0x40 0x1b 0x11
# CHECK: frip 2, 3
0xfc 0x40 0x1b 0x90
# CHECK: frip. 2, 3
0xfc 0x40 0x1b 0x91
# CHECK: friz 2, 3
0xfc 0x40 0x1b 0x50
# CHECK: friz. 2, 3
0xfc 0x40 0x1b 0x51
# CHECK: frim 2, 3
0xfc 0x40 0x1b 0xd0
# CHECK: frim. 2, 3
0xfc 0x40 0x1b 0xd1
[PowerPC] Implement missing ISA 2.06 instructions. Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement them and add corresponding test cases in this patch. llvm-svn: 291116
2017-01-05 23:00:45 +08:00
# CHECK: ftdiv 2, 3, 4
0xfd 0x03 0x21 0x00
#CHECK: ftsqrt 2, 3
0xfd,0x00,0x19,0x40
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# CHECK: fcmpu 2, 3, 4
0xfd 0x03 0x20 0x00
# CHECK: fsel 2, 3, 4, 5
0xfc 0x43 0x29 0x2e
# CHECK: fsel. 2, 3, 4, 5
0xfc 0x43 0x29 0x2f
# CHECK: mffs 2
0xfc 0x40 0x04 0x8e
[PowerPC] Add assembler support for mcrfs and friends Fill out our support for the floating-point status and control register instructions (mcrfs and friends). As it turns out, these are necessary for compiling src/test/harness_fp.h in TBB for PowerPC. Thanks to Raf Schietekat for reporting the issue! llvm-svn: 226070
2015-01-15 09:00:53 +08:00
# CHECK: mffs. 7
0xfc 0xe0 0x04 0x8f
[Power9] Add new instructions for floating point status and control registers. Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl Differential Revision: https://reviews.llvm.org/D37167 llvm-svn: 311903
2017-08-29 02:46:01 +08:00
# CHECK: mffsce 2
0xfc 0x41 0x04 0x8e
# CHECK: mffscdrn 2, 3
0xfc 0x54 0x1c 0x8e
# CHECK: mffscdrni 2, 3
0xfc 0x55 0x1c 0x8e
# CHECK: mffscrn 2, 3
0xfc 0x56 0x1c 0x8e
# CHECK: mffscrni 2, 3
0xfc 0x57 0x1c 0x8e
# CHECK: mffsl 2
0xfc 0x58 0x04 0x8e
[PowerPC] Add assembler support for mcrfs and friends Fill out our support for the floating-point status and control register instructions (mcrfs and friends). As it turns out, these are necessary for compiling src/test/harness_fp.h in TBB for PowerPC. Thanks to Raf Schietekat for reporting the issue! llvm-svn: 226070
2015-01-15 09:00:53 +08:00
# CHECK: mcrfs 4, 5
0xfe 0x14 0x00 0x80
# CHECK: mtfsfi 5, 2, 1
0xfe 0x81 0x21 0x0c
# CHECK: mtfsfi. 5, 2, 1
0xfe 0x81 0x21 0x0d
# CHECK: mtfsf 127, 8, 1, 1
0xfe 0xff 0x45 0x8e
# CHECK: mtfsf. 125, 8, 1, 1
0xfe 0xfb 0x45 0x8f
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# CHECK: mtfsb0 31
0xff 0xe0 0x00 0x8c
# CHECK: mtfsb1 31
0xff 0xe0 0x00 0x4c