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llvm-project/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt

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Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
[PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev These few book-III instructions are used by the Linux kernel. Partially fixes PR24796. llvm-svn: 280560
2016-09-03 07:42:01 +08:00
# CHECK: hrfid
0x4c 0x00 0x02 0x24
# CHECK: nap
0x4c 0x00 0x03 0x64
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-24 02:30:38 +08:00
# CHECK: mtmsr 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
0x7c 0x80 0x01 0x24
# CHECK: mtmsr 4, 1
0x7c 0x81 0x01 0x24
# CHECK: mfmsr 4
0x7c 0x80 0x00 0xa6
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-24 02:30:38 +08:00
# CHECK: mtmsrd 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
0x7c 0x80 0x01 0x64
# CHECK: mtmsrd 4, 1
0x7c 0x81 0x01 0x64
# CHECK: mfspr 4, 272
0x7c 0x90 0x42 0xa6
# CHECK: mfspr 4, 273
0x7c 0x91 0x42 0xa6
# CHECK: mfspr 4, 274
0x7c 0x92 0x42 0xa6
# CHECK: mfspr 4, 275
0x7c 0x93 0x42 0xa6
# CHECK: mtspr 272, 4
0x7c 0x90 0x43 0xa6
# CHECK: mtspr 273, 4
0x7c 0x91 0x43 0xa6
# CHECK: mtspr 274, 4
0x7c 0x92 0x43 0xa6
# CHECK: mtspr 275, 4
0x7c 0x93 0x43 0xa6
# CHECK: mtspr 272, 4
0x7c 0x90 0x43 0xa6
# CHECK: mtspr 273, 4
0x7c 0x91 0x43 0xa6
# CHECK: mtspr 274, 4
0x7c 0x92 0x43 0xa6
# CHECK: mtspr 275, 4
0x7c 0x93 0x43 0xa6
# CHECK: mtspr 280, 4
0x7c 0x98 0x43 0xa6
# CHECK: mfspr 4, 22
0x7c 0x96 0x02 0xa6
# CHECK: mtspr 22, 4
0x7c 0x96 0x03 0xa6
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-24 02:30:38 +08:00
# CHECK: mfpvr 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
0x7c 0x9f 0x42 0xa6
# CHECK: mfspr 4, 25
0x7c 0x99 0x02 0xa6
# CHECK: mtspr 25, 4
0x7c 0x99 0x03 0xa6
# CHECK: mfspr 4, 26
0x7c 0x9a 0x02 0xa6
# CHECK: mtspr 26, 4
0x7c 0x9a 0x03 0xa6
# CHECK: mfspr 4, 27
0x7c 0x9b 0x02 0xa6
# CHECK: mtspr 27, 4
0x7c 0x9b 0x03 0xa6
# CHECK: slbie 4
0x7c 0x00 0x23 0x64
# CHECK: slbmte 4, 5
0x7c 0x80 0x2b 0x24
# CHECK: slbmfee 4, 5
0x7c 0x80 0x2f 0x26
[PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev These few book-III instructions are used by the Linux kernel. Partially fixes PR24796. llvm-svn: 280560
2016-09-03 07:42:01 +08:00
0x7c 0x40 0x1e 0xa6
# CHECK: slbmfev 2, 3
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
# CHECK: slbia
0x7c 0x00 0x03 0xe4
# CHECK: tlbsync
0x7c 0x00 0x04 0x6c
# CHECK: tlbiel 4
0x7c 0x00 0x22 0x24
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-24 02:30:38 +08:00
# CHECK: tlbie 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
0x7c 0x00 0x22 0x64
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-24 02:30:38 +08:00
# CHECK: tlbie 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
2013-12-20 00:13:01 +08:00
0x7c 0x00 0x22 0x64
Add rfi instruction. Based on feedback by Ulrich Weigand. llvm-svn: 214181
2014-07-29 23:49:09 +08:00
# CHECK: rfi
0x4c 0x00 0x00 0x64
Add rfci instruction. llvm-svn: 214256
2014-07-30 07:45:20 +08:00
# CHECK: rfci
0x4c 0x00 0x00 0x66
Add BookE's wrtee and wrteei instructions. llvm-svn: 214297
2014-07-30 18:32:51 +08:00
# CHECK: wrtee 12
0x7d 0x80 0x01 0x06
# CHECK: wrteei 0
0x7c 0x00 0x01 0x46
# CHECK: wrteei 1
0x7c 0x00 0x81 0x46
Add BookE's tlbre, tlbwe and tlbivax instructions. llvm-svn: 214332
2014-07-31 04:44:04 +08:00
# CHECK: tlbre
0x7c 0x00 0x07 0x64
# CHECK: tlbwe
0x7c 0x00 0x07 0xa4
# CHECK: tlbivax 11, 12
0x7c 0x0b 0x66 0x24
Refactor TLBIVAX and add tlbsx. llvm-svn: 214354
2014-07-31 06:51:15 +08:00
# CHECK: tlbsx 11, 12
0x7c 0x0b 0x67 0x24
Add some Book-E instructions to the asm parser and printer. Summary: Adds the following instructions: * mfpmr * mtpmr * icblc * icblq * icbtls Fix the scheduling for mtspr on e5500, which uses CFX0, instead of SFX0/SFX1 as on e500mc. Addresses PR 31538. Differential Revision: https://reviews.llvm.org/D29002 llvm-svn: 293417
2017-01-29 12:55:57 +08:00
# CHECK: mfpmr 5, 400
0x7c 0xb0 0x62 0x9c
# CHECK: mtpmr 400, 6
0x7c 0xd0 0x63 0x9c
# CHECK: icblc 0, 0, 8
0x7c 0x00 0x41 0xcc
# CHECK: icbtls 0, 0, 9
0x7c 0x00 0x4b 0xcc