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llvm-project/llvm/test/MC/AArch64/SVE/sqincp.s

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[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqincp x0, p0.b
// CHECK-INST: sqincp x0, p0.b
// CHECK-ENCODING: [0x00,0x8c,0x28,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 8c 28 25 <unknown>
sqincp x0, p0.h
// CHECK-INST: sqincp x0, p0.h
// CHECK-ENCODING: [0x00,0x8c,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 8c 68 25 <unknown>
sqincp x0, p0.s
// CHECK-INST: sqincp x0, p0.s
// CHECK-ENCODING: [0x00,0x8c,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 8c a8 25 <unknown>
sqincp x0, p0.d
// CHECK-INST: sqincp x0, p0.d
// CHECK-ENCODING: [0x00,0x8c,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 8c e8 25 <unknown>
sqincp xzr, p15.b, wzr
// CHECK-INST: sqincp xzr, p15.b, wzr
// CHECK-ENCODING: [0xff,0x89,0x28,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 28 25 <unknown>
sqincp xzr, p15.h, wzr
// CHECK-INST: sqincp xzr, p15.h, wzr
// CHECK-ENCODING: [0xff,0x89,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 68 25 <unknown>
sqincp xzr, p15.s, wzr
// CHECK-INST: sqincp xzr, p15.s, wzr
// CHECK-ENCODING: [0xff,0x89,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 a8 25 <unknown>
sqincp xzr, p15.d, wzr
// CHECK-INST: sqincp xzr, p15.d, wzr
// CHECK-ENCODING: [0xff,0x89,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 e8 25 <unknown>
sqincp z0.h, p0
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
// CHECK-INST: sqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.h, p0.h
// CHECK-INST: sqincp z0.h, p0.h
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.s, p0
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
// CHECK-INST: sqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.s, p0.s
// CHECK-INST: sqincp z0.s, p0.s
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.d, p0
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
sqincp z0.d, p0.d
// CHECK-INST: sqincp z0.d, p0.d
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
sqincp z0.d, p0.d
// CHECK-INST: sqincp z0.d, p0.d
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>