2018-05-08 18:46:55 +08:00
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid immediate (in range [0, 63]).
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ld1rsb z0.h, p1/z, [x0, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
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// CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rsb z0.h, p1/z, [x0, #64]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
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// CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #64]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid result vector element size
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ld1rsb z0.b, p1/z, [x0]
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[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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2018-05-08 18:46:55 +08:00
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// CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ld1rsb z0.h, p8/z, [x0]
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2019-06-07 16:37:00 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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2018-05-08 18:46:55 +08:00
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// CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2018-07-31 00:05:45 +08:00
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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