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llvm-project/llvm/test/MC/AArch64/SVE/incp.s

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[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
incp x0, p0.b
// CHECK-INST: incp x0, p0.b
// CHECK-ENCODING: [0x00,0x88,0x2c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 88 2c 25 <unknown>
incp x0, p0.h
// CHECK-INST: incp x0, p0.h
// CHECK-ENCODING: [0x00,0x88,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 88 6c 25 <unknown>
incp x0, p0.s
// CHECK-INST: incp x0, p0.s
// CHECK-ENCODING: [0x00,0x88,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 88 ac 25 <unknown>
incp x0, p0.d
// CHECK-INST: incp x0, p0.d
// CHECK-ENCODING: [0x00,0x88,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 88 ec 25 <unknown>
incp xzr, p15.b
// CHECK-INST: incp xzr, p15.b
// CHECK-ENCODING: [0xff,0x89,0x2c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 2c 25 <unknown>
incp xzr, p15.h
// CHECK-INST: incp xzr, p15.h
// CHECK-ENCODING: [0xff,0x89,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 6c 25 <unknown>
incp xzr, p15.s
// CHECK-INST: incp xzr, p15.s
// CHECK-ENCODING: [0xff,0x89,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 ac 25 <unknown>
incp xzr, p15.d
// CHECK-INST: incp xzr, p15.d
// CHECK-ENCODING: [0xff,0x89,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 ec 25 <unknown>
incp z31.h, p15
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
// CHECK-INST: incp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.h, p15.h
// CHECK-INST: incp z31.h, p15.h
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.s, p15
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
// CHECK-INST: incp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.s, p15.s
// CHECK-INST: incp z31.s, p15.s
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.d, p15
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
incp z31.d, p15.d
// CHECK-INST: incp z31.d, p15.d
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) Increments/decrements the result with the number of active bits from the predicate. The inc/dec variants added are: - incp x0, p0.h (scalar) - incp z0.h, p0 (vector) The unsigned saturating inc/dec variants added are: - uqincp x0, p0.h (scalar) - uqincp w0, p0.h (scalar, 32bit) - uqincp z0.h, p0 (vector) The signed saturating inc/dec variants added are: - sqincp x0, p0.h (scalar) - sqincp x0, p0.h, w0 (scalar, 32bit) - sqincp z0.h, p0 (vector) llvm-svn: 336091
2018-07-02 18:08:36 +08:00
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
[AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
2019-07-25 21:56:04 +08:00
incp z31.d, p15.d
// CHECK-INST: incp z31.d, p15.d
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>