2015-11-27 00:54:33 +08:00
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//=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V60 Compiler Intrinsics in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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2016-04-23 02:05:55 +08:00
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2015-11-27 00:54:33 +08:00
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let AddedComplexity = 100 in {
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def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
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2016-11-10 00:19:08 +08:00
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(v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_lo)) >,
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2015-11-27 00:54:33 +08:00
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Requires<[UseHVXSgl]>;
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def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
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2016-11-10 00:19:08 +08:00
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(v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_hi)) >,
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2015-11-27 00:54:33 +08:00
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Requires<[UseHVXSgl]>;
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def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
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2016-11-10 00:19:08 +08:00
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(v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_lo)) >,
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2015-11-27 00:54:33 +08:00
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Requires<[UseHVXDbl]>;
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def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
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2016-11-10 00:19:08 +08:00
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(v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_hi)) >,
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2015-11-27 00:54:33 +08:00
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Requires<[UseHVXDbl]>;
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}
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def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
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(v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
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(v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
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(v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
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(v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
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(v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
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(v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
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(v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
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(v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
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(v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
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(v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
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(v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
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(v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
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(v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
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(v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
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(v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
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(v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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let AddedComplexity = 140 in {
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def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
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(V6_vS32b_ai IntRegs:$addr, 0,
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(v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
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(A2_tfrsi 0x01010101))))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
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(v512i1 (V6_vandvrt
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(v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXSgl]>;
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def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
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(V6_vS32b_ai_128B IntRegs:$addr, 0,
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(v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
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(A2_tfrsi 0x01010101))))>,
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Requires<[UseHVXDbl]>;
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def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
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(v1024i1 (V6_vandvrt_128B
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(v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
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(A2_tfrsi 0x01010101)))>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
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(!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1),
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(MI VectorRegs:$src1)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>,
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Requires<[UseHVXDbl]>;
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}
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2016-08-17 01:14:44 +08:00
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multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1),
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(MI VecDblRegs:$src1)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1)>,
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Requires<[UseHVXDbl]>;
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}
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2015-11-27 00:54:33 +08:00
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multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecPredRegs:$src1),
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(MI VecPredRegs:$src1)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
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(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
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(MI VecDblRegs:$src1, IntRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
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(!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
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(MI VectorRegs:$src1, IntRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
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(!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
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(MI VecDblRegs:$src1, VectorRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
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VectorRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
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VectorRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
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(MI VecDblRegs:$src1, VecDblRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
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VecDblRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
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VecDblRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
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(MI VectorRegs:$src1, VectorRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
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VectorRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
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VectorRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
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(MI VecPredRegs:$src1, IntRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
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IntRegs:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
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IntRegs:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
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(MI VecPredRegs:$src1, VecPredRegs:$src2)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
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VecPredRegs128B:$src2),
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(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
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VecPredRegs128B:$src2)>,
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Requires<[UseHVXDbl]>;
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}
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multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
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(MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
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Requires<[UseHVXSgl]>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
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|
|
|
VecDblRegs128B:$src2,
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|
|
IntRegs:$src3),
|
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|
|
|
(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
|
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|
|
|
VecDblRegs128B:$src2,
|
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|
|
|
IntRegs:$src3)>,
|
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|
|
|
Requires<[UseHVXDbl]>;
|
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|
|
|
}
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|
multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
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|
|
|
(MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
|
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|
|
|
Requires<[UseHVXSgl]>;
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|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
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|
VectorRegs128B:$src2,
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|
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|
IntRegs:$src3),
|
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|
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|
(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
|
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|
|
|
VectorRegs128B:$src2,
|
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|
|
|
IntRegs:$src3)>,
|
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|
|
|
Requires<[UseHVXDbl]>;
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|
}
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multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
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|
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|
(MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
|
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|
|
|
Requires<[UseHVXSgl]>;
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|
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|
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|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
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|
VectorRegs128B:$src2,
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|
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|
IntRegs:$src3),
|
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|
|
|
(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
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|
|
|
IntRegs:$src3)>,
|
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|
|
|
Requires<[UseHVXDbl]>;
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|
}
|
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|
|
multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
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|
def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
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|
|
|
(MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
|
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|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
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|
|
|
VecDblRegs128B:$src2,
|
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|
|
|
IntRegs:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VecDblRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
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|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
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|
|
|
def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
|
|
|
|
|
(MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
|
|
|
|
|
(MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
|
|
|
|
|
(MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
|
|
|
|
|
(MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VecPredRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VecPredRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
|
|
|
|
|
(MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
|
|
|
|
|
(MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2, imm:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2, imm:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
|
|
|
|
|
(MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
IntRegs:$src2, imm:$src3),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
IntRegs:$src2, imm:$src3)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
|
|
|
|
|
(MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VecDblRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3, imm:$src4),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VecDblRegs128B:$src2,
|
|
|
|
|
IntRegs:$src3, imm:$src4)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
|
|
|
|
|
IntRegs:$src4),
|
|
|
|
|
(MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
|
|
|
|
|
IntRegs:$src4)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3,
|
|
|
|
|
IntRegs:$src4),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3,
|
|
|
|
|
IntRegs:$src4)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
|
|
|
|
|
def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
|
|
|
|
|
IntRegs:$src4),
|
|
|
|
|
(MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
|
|
|
|
|
IntRegs:$src4)>,
|
|
|
|
|
Requires<[UseHVXSgl]>;
|
|
|
|
|
|
|
|
|
|
def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3,
|
|
|
|
|
IntRegs:$src4),
|
|
|
|
|
(!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
|
|
|
|
|
VectorRegs128B:$src2,
|
|
|
|
|
VectorRegs128B:$src3,
|
|
|
|
|
IntRegs:$src4)>,
|
|
|
|
|
Requires<[UseHVXDbl]>;
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-17 01:14:44 +08:00
|
|
|
defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>;
|
2015-11-27 00:54:33 +08:00
|
|
|
defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>;
|
|
|
|
|
defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>;
|
|
|
|
|
defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>;
|
|
|
|
|
defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>;
|
|
|
|
|
defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>;
|
|
|
|
|
defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>;
|
|
|
|
|
defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>;
|
|
|
|
|
defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>;
|
|
|
|
|
defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>;
|
|
|
|
|
defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>;
|
|
|
|
|
defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>;
|
|
|
|
|
defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>;
|
|
|
|
|
defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>;
|
|
|
|
|
defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>;
|
|
|
|
|
defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>;
|
|
|
|
|
defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>;
|
|
|
|
|
defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>;
|
|
|
|
|
defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>;
|
|
|
|
|
defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>;
|
|
|
|
|
defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>;
|
|
|
|
|
defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>;
|
|
|
|
|
defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>;
|
|
|
|
|
defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>;
|
|
|
|
|
|
|
|
|
|
defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>;
|
|
|
|
|
defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>;
|
|
|
|
|
defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>;
|
|
|
|
|
defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>;
|
|
|
|
|
defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>;
|
|
|
|
|
defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>;
|
|
|
|
|
defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>;
|
|
|
|
|
defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>;
|
|
|
|
|
defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>;
|
|
|
|
|
defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>;
|
|
|
|
|
defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>;
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defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>;
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defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>;
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defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>;
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defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>;
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defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>;
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defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>;
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defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>;
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defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>;
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defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>;
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defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>;
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defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>;
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defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>;
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defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>;
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defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>;
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defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>;
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defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>;
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defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>;
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defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>;
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defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>;
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defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>;
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defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>;
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defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>;
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defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>;
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defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>;
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defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>;
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defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>;
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defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>;
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defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>;
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defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>;
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defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>;
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defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>;
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defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>;
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defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>;
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defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>;
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defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>;
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defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>;
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defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>;
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defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>;
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defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>;
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defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>;
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defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>;
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defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>;
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defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>;
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defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>;
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defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>;
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defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>;
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defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>;
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defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>;
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defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>;
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defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>;
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defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>;
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defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>;
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defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>;
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defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>;
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defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>;
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defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>;
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defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>;
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defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>;
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defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>;
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defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>;
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defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>;
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defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>;
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defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>;
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defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>;
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defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>;
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defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>;
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defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>;
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defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>;
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defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>;
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defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>;
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defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>;
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defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>;
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defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>;
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defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>;
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defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>;
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defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>;
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defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>;
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defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>;
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defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>;
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defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>;
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defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>;
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defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>;
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defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>;
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defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>;
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defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>;
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defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>;
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// Compare instructions
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defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>;
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defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>;
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defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>;
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defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>;
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defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>;
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defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>;
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defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>;
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defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>;
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defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>;
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defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>;
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defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>;
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defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>;
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defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>;
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defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>;
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defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>;
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defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>;
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defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>;
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defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>;
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defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>;
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defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>;
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defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>;
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defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>;
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defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>;
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defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>;
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defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>;
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defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>;
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defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>;
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defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>;
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defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>;
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defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>;
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defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>;
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defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>;
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defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>;
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defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>;
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defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>;
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defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>;
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defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>;
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defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>;
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defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>;
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defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>;
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defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>;
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defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>;
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defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>;
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defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>;
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defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>;
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defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>;
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defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>;
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defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>;
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defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>;
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defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>;
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defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>;
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defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>;
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defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>;
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defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>;
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defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>;
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defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>;
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defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>;
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defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>;
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defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>;
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defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>;
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defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>;
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defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>;
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defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>;
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defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>;
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defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>;
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defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>;
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defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>;
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defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>;
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defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>;
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defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>;
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defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>;
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defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>;
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defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>;
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defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>;
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defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>;
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defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>;
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defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>;
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defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>;
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defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>;
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defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>;
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defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>;
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defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>;
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defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>;
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defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>;
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defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>;
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defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>;
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defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>;
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defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>;
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defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>;
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defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>;
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defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>;
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defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>;
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defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>;
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defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>;
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defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>;
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defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>;
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defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>;
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defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>;
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defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>;
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defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>;
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defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>;
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defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>;
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defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>;
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defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>;
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defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>;
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defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>;
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defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>;
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defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>;
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2016-08-17 01:14:44 +08:00
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defm : T_W_pat <V6_lo, int_hexagon_V6_lo>;
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defm : T_W_pat <V6_hi, int_hexagon_V6_hi>;
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defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>;
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2015-11-27 00:54:33 +08:00
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defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>;
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defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>;
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defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>;
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defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>;
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defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>;
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defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>;
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// assembler mapped.
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//defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>;
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// not present earlier.. need to add intrinsic
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defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>;
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defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>;
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defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>;
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defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>;
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defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>;
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defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>;
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defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>;
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defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>;
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defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>;
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defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>;
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defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>;
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defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>;
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defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>;
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defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>;
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defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>;
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defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>;
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defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>;
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defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>;
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defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>;
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defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>;
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defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>;
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defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>;
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defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>;
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defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>;
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defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>;
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defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>;
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defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>;
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defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>;
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defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>;
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defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>;
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defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>;
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defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>;
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defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>;
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defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
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defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>;
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defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>;
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2016-04-23 02:05:55 +08:00
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defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>;
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2015-11-27 00:54:33 +08:00
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defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>;
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defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>;
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defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>;
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defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>;
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defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>;
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defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
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def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>;
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def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>;
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def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>;
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def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>;
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def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>;
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def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>;
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def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>;
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def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>;
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def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>;
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def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>;
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def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>;
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def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>;
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defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>;
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defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
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2017-02-10 23:33:13 +08:00
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//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
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2015-11-27 00:54:33 +08:00
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def: Pat<(v64i16 (trunc v64i32:$Vdd)),
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(v64i16 (V6_vpackwh_sat_128B
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2016-08-17 01:14:44 +08:00
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(v32i32 (V6_hi_128B VecDblRegs128B:$Vdd)),
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(v32i32 (V6_lo_128B VecDblRegs128B:$Vdd))))>,
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2015-11-27 00:54:33 +08:00
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Requires<[UseHVXDbl]>;
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2016-08-17 01:14:44 +08:00
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def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>;
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def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0_128B)>;
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2015-11-27 00:54:33 +08:00
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