2017-01-12 06:35:17 +08:00
|
|
|
# RUN: llc -verify-machineinstrs -march=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
|
|
|
|
# Check that add with carry out isn't incorrectly reduced to e32 when
|
|
|
|
# the carry out is a virtual register.
|
|
|
|
|
|
|
|
# TODO: We should run this test until the end of codegen to make sure
|
|
|
|
# that the post-RA run does manage to shrink it, but right now the
|
|
|
|
# resume crashes
|
|
|
|
|
|
|
|
...
|
|
|
|
# GCN-LABEL: name: shrink_add_vop3{{$}}
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
name: shrink_add_vop3
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 1
|
2017-01-12 06:35:17 +08:00
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: false
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: sgpr_64 }
|
|
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
|
|
- { id: 2, class: sgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: sreg_64_xexec }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: sreg_32 }
|
|
|
|
- { id: 7, class: sreg_32 }
|
|
|
|
- { id: 8, class: sreg_32_xm0 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 9, class: sreg_64_xexec }
|
2017-01-12 06:35:17 +08:00
|
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
|
|
- { id: 12, class: sgpr_64 }
|
|
|
|
- { id: 13, class: sgpr_128 }
|
|
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
|
|
- { id: 15, class: sreg_64 }
|
|
|
|
- { id: 16, class: sgpr_128 }
|
|
|
|
- { id: 17, class: vgpr_32 }
|
|
|
|
- { id: 18, class: vreg_64 }
|
|
|
|
- { id: 19, class: vgpr_32 }
|
|
|
|
- { id: 20, class: vreg_64 }
|
|
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
|
|
- { id: 22, class: sreg_32 }
|
|
|
|
- { id: 23, class: sreg_32 }
|
|
|
|
- { id: 24, class: vgpr_32 }
|
|
|
|
- { id: 25, class: vreg_64 }
|
|
|
|
- { id: 26, class: vgpr_32 }
|
|
|
|
- { id: 27, class: vreg_64 }
|
|
|
|
- { id: 28, class: vreg_64 }
|
|
|
|
- { id: 29, class: vgpr_32 }
|
|
|
|
liveins:
|
2018-02-01 06:04:26 +08:00
|
|
|
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
|
- { reg: '$vgpr0', virtual-reg: '%3' }
|
2017-01-12 06:35:17 +08:00
|
|
|
frameInfo:
|
|
|
|
isFrameAddressTaken: false
|
|
|
|
isReturnAddressTaken: false
|
|
|
|
hasStackMap: false
|
|
|
|
hasPatchPoint: false
|
|
|
|
stackSize: 0
|
|
|
|
offsetAdjustment: 0
|
|
|
|
maxAlignment: 0
|
|
|
|
adjustsStack: false
|
|
|
|
hasCalls: false
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
hasOpaqueSPAdjustment: false
|
|
|
|
hasVAStart: false
|
|
|
|
hasMustTailInVarArgFunc: false
|
|
|
|
body: |
|
2017-07-07 04:56:57 +08:00
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $vgpr0
|
2017-01-12 06:35:17 +08:00
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = COPY $vgpr0
|
|
|
|
%0 = COPY $sgpr0_sgpr1
|
2019-05-01 06:08:23 +08:00
|
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
|
%10 = S_MOV_B32 61440
|
|
|
|
%11 = S_MOV_B32 0
|
|
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
2018-02-01 06:04:26 +08:00
|
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%29, %9 = V_ADD_I32_e64 %19, %17, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
|
|
|
S_ENDPGM 0
|
2017-01-12 06:35:17 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
# GCN-LABEL: name: shrink_sub_vop3{{$}}
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
|
|
|
|
name: shrink_sub_vop3
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 1
|
2017-01-12 06:35:17 +08:00
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: false
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: sgpr_64 }
|
|
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
|
|
- { id: 2, class: sgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: sreg_64_xexec }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: sreg_32 }
|
|
|
|
- { id: 7, class: sreg_32 }
|
|
|
|
- { id: 8, class: sreg_32_xm0 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 9, class: sreg_64_xexec }
|
2017-01-12 06:35:17 +08:00
|
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
|
|
- { id: 12, class: sgpr_64 }
|
|
|
|
- { id: 13, class: sgpr_128 }
|
|
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
|
|
- { id: 15, class: sreg_64 }
|
|
|
|
- { id: 16, class: sgpr_128 }
|
|
|
|
- { id: 17, class: vgpr_32 }
|
|
|
|
- { id: 18, class: vreg_64 }
|
|
|
|
- { id: 19, class: vgpr_32 }
|
|
|
|
- { id: 20, class: vreg_64 }
|
|
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
|
|
- { id: 22, class: sreg_32 }
|
|
|
|
- { id: 23, class: sreg_32 }
|
|
|
|
- { id: 24, class: vgpr_32 }
|
|
|
|
- { id: 25, class: vreg_64 }
|
|
|
|
- { id: 26, class: vgpr_32 }
|
|
|
|
- { id: 27, class: vreg_64 }
|
|
|
|
- { id: 28, class: vreg_64 }
|
|
|
|
- { id: 29, class: vgpr_32 }
|
|
|
|
liveins:
|
2018-02-01 06:04:26 +08:00
|
|
|
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
|
- { reg: '$vgpr0', virtual-reg: '%3' }
|
2017-01-12 06:35:17 +08:00
|
|
|
frameInfo:
|
|
|
|
isFrameAddressTaken: false
|
|
|
|
isReturnAddressTaken: false
|
|
|
|
hasStackMap: false
|
|
|
|
hasPatchPoint: false
|
|
|
|
stackSize: 0
|
|
|
|
offsetAdjustment: 0
|
|
|
|
maxAlignment: 0
|
|
|
|
adjustsStack: false
|
|
|
|
hasCalls: false
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
hasOpaqueSPAdjustment: false
|
|
|
|
hasVAStart: false
|
|
|
|
hasMustTailInVarArgFunc: false
|
|
|
|
body: |
|
2017-07-07 04:56:57 +08:00
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $vgpr0
|
2017-01-12 06:35:17 +08:00
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = COPY $vgpr0
|
|
|
|
%0 = COPY $sgpr0_sgpr1
|
2019-05-01 06:08:23 +08:00
|
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
|
%10 = S_MOV_B32 61440
|
|
|
|
%11 = S_MOV_B32 0
|
|
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
2018-02-01 06:04:26 +08:00
|
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%29, %9 = V_SUB_I32_e64 %19, %17, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
|
|
|
S_ENDPGM 0
|
2017-01-12 06:35:17 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
# GCN-LABEL: name: shrink_subrev_vop3{{$}}
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
|
|
|
|
name: shrink_subrev_vop3
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 1
|
2017-01-12 06:35:17 +08:00
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: false
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: sgpr_64 }
|
|
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
|
|
- { id: 2, class: sgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: sreg_64_xexec }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: sreg_32 }
|
|
|
|
- { id: 7, class: sreg_32 }
|
|
|
|
- { id: 8, class: sreg_32_xm0 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 9, class: sreg_64_xexec }
|
2017-01-12 06:35:17 +08:00
|
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
|
|
- { id: 12, class: sgpr_64 }
|
|
|
|
- { id: 13, class: sgpr_128 }
|
|
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
|
|
- { id: 15, class: sreg_64 }
|
|
|
|
- { id: 16, class: sgpr_128 }
|
|
|
|
- { id: 17, class: vgpr_32 }
|
|
|
|
- { id: 18, class: vreg_64 }
|
|
|
|
- { id: 19, class: vgpr_32 }
|
|
|
|
- { id: 20, class: vreg_64 }
|
|
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
|
|
- { id: 22, class: sreg_32 }
|
|
|
|
- { id: 23, class: sreg_32 }
|
|
|
|
- { id: 24, class: vgpr_32 }
|
|
|
|
- { id: 25, class: vreg_64 }
|
|
|
|
- { id: 26, class: vgpr_32 }
|
|
|
|
- { id: 27, class: vreg_64 }
|
|
|
|
- { id: 28, class: vreg_64 }
|
|
|
|
- { id: 29, class: vgpr_32 }
|
|
|
|
liveins:
|
2018-02-01 06:04:26 +08:00
|
|
|
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
|
- { reg: '$vgpr0', virtual-reg: '%3' }
|
2017-01-12 06:35:17 +08:00
|
|
|
frameInfo:
|
|
|
|
isFrameAddressTaken: false
|
|
|
|
isReturnAddressTaken: false
|
|
|
|
hasStackMap: false
|
|
|
|
hasPatchPoint: false
|
|
|
|
stackSize: 0
|
|
|
|
offsetAdjustment: 0
|
|
|
|
maxAlignment: 0
|
|
|
|
adjustsStack: false
|
|
|
|
hasCalls: false
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
hasOpaqueSPAdjustment: false
|
|
|
|
hasVAStart: false
|
|
|
|
hasMustTailInVarArgFunc: false
|
|
|
|
body: |
|
2017-07-07 04:56:57 +08:00
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $vgpr0
|
2017-01-12 06:35:17 +08:00
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = COPY $vgpr0
|
|
|
|
%0 = COPY $sgpr0_sgpr1
|
2019-05-01 06:08:23 +08:00
|
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
|
%10 = S_MOV_B32 61440
|
|
|
|
%11 = S_MOV_B32 0
|
|
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
2018-02-01 06:04:26 +08:00
|
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
2017-01-12 06:35:17 +08:00
|
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%29, %9 = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
|
|
|
S_ENDPGM 0
|
2017-01-12 06:35:17 +08:00
|
|
|
|
|
|
|
...
|
2017-01-12 06:58:12 +08:00
|
|
|
---
|
|
|
|
# GCN-LABEL: name: check_addc_src2_vop3{{$}}
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
name: check_addc_src2_vop3
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 1
|
2017-01-12 06:58:12 +08:00
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: false
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: sgpr_64 }
|
|
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
|
|
- { id: 2, class: sgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: sreg_64_xexec }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: sreg_32 }
|
|
|
|
- { id: 7, class: sreg_32 }
|
|
|
|
- { id: 8, class: sreg_32_xm0 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 9, class: sreg_64_xexec }
|
2017-01-12 06:58:12 +08:00
|
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
|
|
- { id: 12, class: sgpr_64 }
|
|
|
|
- { id: 13, class: sgpr_128 }
|
|
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
|
|
- { id: 15, class: sreg_64 }
|
|
|
|
- { id: 16, class: sgpr_128 }
|
|
|
|
- { id: 17, class: vgpr_32 }
|
|
|
|
- { id: 18, class: vreg_64 }
|
|
|
|
- { id: 19, class: vgpr_32 }
|
|
|
|
- { id: 20, class: vreg_64 }
|
|
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
|
|
- { id: 22, class: sreg_32 }
|
|
|
|
- { id: 23, class: sreg_32 }
|
|
|
|
- { id: 24, class: vgpr_32 }
|
|
|
|
- { id: 25, class: vreg_64 }
|
|
|
|
- { id: 26, class: vgpr_32 }
|
|
|
|
- { id: 27, class: vreg_64 }
|
|
|
|
- { id: 28, class: vreg_64 }
|
|
|
|
- { id: 29, class: vgpr_32 }
|
|
|
|
liveins:
|
2018-02-01 06:04:26 +08:00
|
|
|
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
|
- { reg: '$vgpr0', virtual-reg: '%3' }
|
2017-01-12 06:58:12 +08:00
|
|
|
frameInfo:
|
|
|
|
isFrameAddressTaken: false
|
|
|
|
isReturnAddressTaken: false
|
|
|
|
hasStackMap: false
|
|
|
|
hasPatchPoint: false
|
|
|
|
stackSize: 0
|
|
|
|
offsetAdjustment: 0
|
|
|
|
maxAlignment: 0
|
|
|
|
adjustsStack: false
|
|
|
|
hasCalls: false
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
hasOpaqueSPAdjustment: false
|
|
|
|
hasVAStart: false
|
|
|
|
hasMustTailInVarArgFunc: false
|
|
|
|
body: |
|
2017-07-07 04:56:57 +08:00
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $vgpr0
|
2017-01-12 06:58:12 +08:00
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = COPY $vgpr0
|
|
|
|
%0 = COPY $sgpr0_sgpr1
|
2019-05-01 06:08:23 +08:00
|
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
|
%10 = S_MOV_B32 61440
|
|
|
|
%11 = S_MOV_B32 0
|
|
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
2018-02-01 06:04:26 +08:00
|
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%9 = S_MOV_B64 0
|
2019-03-19 03:35:44 +08:00
|
|
|
%29, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
|
|
|
S_ENDPGM 0
|
2017-01-12 06:58:12 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
# GCN-LABEL: name: shrink_addc_vop3{{$}}
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
|
|
|
|
name: shrink_addc_vop3
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 1
|
2017-01-12 06:58:12 +08:00
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: false
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: sgpr_64 }
|
|
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
|
|
- { id: 2, class: sgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: sreg_64_xexec }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: sreg_32 }
|
|
|
|
- { id: 7, class: sreg_32 }
|
|
|
|
- { id: 8, class: sreg_32_xm0 }
|
|
|
|
- { id: 9, class: sreg_64 }
|
|
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
|
|
- { id: 12, class: sgpr_64 }
|
|
|
|
- { id: 13, class: sgpr_128 }
|
|
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
|
|
- { id: 15, class: sreg_64 }
|
|
|
|
- { id: 16, class: sgpr_128 }
|
|
|
|
- { id: 17, class: vgpr_32 }
|
|
|
|
- { id: 18, class: vreg_64 }
|
|
|
|
- { id: 19, class: vgpr_32 }
|
|
|
|
- { id: 20, class: vreg_64 }
|
|
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
|
|
- { id: 22, class: sreg_32 }
|
|
|
|
- { id: 23, class: sreg_32 }
|
|
|
|
- { id: 24, class: vgpr_32 }
|
|
|
|
- { id: 25, class: vreg_64 }
|
|
|
|
- { id: 26, class: vgpr_32 }
|
|
|
|
- { id: 27, class: vreg_64 }
|
|
|
|
- { id: 28, class: vreg_64 }
|
|
|
|
- { id: 29, class: vgpr_32 }
|
|
|
|
liveins:
|
2018-02-01 06:04:26 +08:00
|
|
|
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
|
- { reg: '$vgpr0', virtual-reg: '%3' }
|
2017-01-12 06:58:12 +08:00
|
|
|
frameInfo:
|
|
|
|
isFrameAddressTaken: false
|
|
|
|
isReturnAddressTaken: false
|
|
|
|
hasStackMap: false
|
|
|
|
hasPatchPoint: false
|
|
|
|
stackSize: 0
|
|
|
|
offsetAdjustment: 0
|
|
|
|
maxAlignment: 0
|
|
|
|
adjustsStack: false
|
|
|
|
hasCalls: false
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
hasOpaqueSPAdjustment: false
|
|
|
|
hasVAStart: false
|
|
|
|
hasMustTailInVarArgFunc: false
|
|
|
|
body: |
|
2017-07-07 04:56:57 +08:00
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $vgpr0
|
2017-01-12 06:58:12 +08:00
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = COPY $vgpr0
|
|
|
|
%0 = COPY $sgpr0_sgpr1
|
2019-05-01 06:08:23 +08:00
|
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
|
%10 = S_MOV_B32 61440
|
|
|
|
%11 = S_MOV_B32 0
|
|
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
2018-02-01 06:04:26 +08:00
|
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
$vcc = S_MOV_B64 0
|
2019-03-19 03:35:44 +08:00
|
|
|
%29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
|
|
|
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
|
|
|
S_ENDPGM 0
|
2017-01-12 06:58:12 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
# GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
name: shrink_addc_undef_vcc
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 1
|
2017-01-12 06:58:12 +08:00
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: false
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: sgpr_64 }
|
|
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
|
|
- { id: 2, class: sgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: sreg_64_xexec }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: sreg_32 }
|
|
|
|
- { id: 7, class: sreg_32 }
|
|
|
|
- { id: 8, class: sreg_32_xm0 }
|
|
|
|
- { id: 9, class: sreg_64 }
|
|
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
|
|
- { id: 12, class: sgpr_64 }
|
|
|
|
- { id: 13, class: sgpr_128 }
|
|
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
|
|
- { id: 15, class: sreg_64 }
|
|
|
|
- { id: 16, class: sgpr_128 }
|
|
|
|
- { id: 17, class: vgpr_32 }
|
|
|
|
- { id: 18, class: vreg_64 }
|
|
|
|
- { id: 19, class: vgpr_32 }
|
|
|
|
- { id: 20, class: vreg_64 }
|
|
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
|
|
- { id: 22, class: sreg_32 }
|
|
|
|
- { id: 23, class: sreg_32 }
|
|
|
|
- { id: 24, class: vgpr_32 }
|
|
|
|
- { id: 25, class: vreg_64 }
|
|
|
|
- { id: 26, class: vgpr_32 }
|
|
|
|
- { id: 27, class: vreg_64 }
|
|
|
|
- { id: 28, class: vreg_64 }
|
|
|
|
- { id: 29, class: vgpr_32 }
|
|
|
|
liveins:
|
2018-02-01 06:04:26 +08:00
|
|
|
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
|
- { reg: '$vgpr0', virtual-reg: '%3' }
|
2017-01-12 06:58:12 +08:00
|
|
|
frameInfo:
|
|
|
|
isFrameAddressTaken: false
|
|
|
|
isReturnAddressTaken: false
|
|
|
|
hasStackMap: false
|
|
|
|
hasPatchPoint: false
|
|
|
|
stackSize: 0
|
|
|
|
offsetAdjustment: 0
|
|
|
|
maxAlignment: 0
|
|
|
|
adjustsStack: false
|
|
|
|
hasCalls: false
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
hasOpaqueSPAdjustment: false
|
|
|
|
hasVAStart: false
|
|
|
|
hasMustTailInVarArgFunc: false
|
|
|
|
body: |
|
2017-07-07 04:56:57 +08:00
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $sgpr0_sgpr1, $vgpr0
|
2017-01-12 06:58:12 +08:00
|
|
|
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = COPY $vgpr0
|
|
|
|
%0 = COPY $sgpr0_sgpr1
|
2019-05-01 06:08:23 +08:00
|
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
|
%10 = S_MOV_B32 61440
|
|
|
|
%11 = S_MOV_B32 0
|
|
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
2018-02-01 06:04:26 +08:00
|
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
2017-01-12 06:58:12 +08:00
|
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
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%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
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2019-03-19 03:35:44 +08:00
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%29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, 0, implicit $exec
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2019-03-19 03:25:39 +08:00
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%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
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[AMDGPU] Extend buffer intrinsics with swizzling
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.
Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store
Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.
The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.
There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.
Reviewers: arsenm, nhaehnle, tpr
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68200
llvm-svn: 373491
2019-10-03 01:22:36 +08:00
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BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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[AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM
Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6
Reviewers: alexshap
Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59213
llvm-svn: 355902
2019-03-12 17:52:58 +08:00
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S_ENDPGM 0
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2017-01-12 06:58:12 +08:00
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...
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