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llvm-project/llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir

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AMDGPU: Fix using unencodable instructions in tests There are a number of MIR tests using instructions on subtargets where they don't really exist. These are some of the easy cases that don't require splitting up test functions.
2020-06-05 03:31:28 +08:00
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
[AMDGPU] Preliminary patch for divergence driven instruction selection. Fold immediate SMRD offset. Differential revision: https://reviews.llvm.org/D51610 Reviewer: rampitec llvm-svn: 341636
2018-09-07 17:05:34 +08:00
AMDGPU: Divergence-driven selection of scalar buffer load intrinsics Summary: Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if the load is really uniform. So select the scalar load intrinsics directly to either VMEM or SMRD buffer loads based on divergence analysis. If an offset happens to end up in a VGPR -- either because a floating point calculation was involved, or due to other remaining deficiencies in SIFixSGPRCopies -- we use v_readfirstlane. There is some unrelated churn in tests since we now select MUBUF offsets in a unified way with non-scalar buffer loads. Change-Id: I170e6816323beb1348677b358c9d380865cd1a19 Reviewers: arsenm, alex-t, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53283 llvm-svn: 348050
2018-12-01 06:55:38 +08:00
# GCN-LABEL: name: smrd_vgpr_offset_imm
# GCN: V_READFIRSTLANE_B32
# GCN: S_BUFFER_LOAD_DWORD_SGPR
[AMDGPU] Preliminary patch for divergence driven instruction selection. Fold immediate SMRD offset. Differential revision: https://reviews.llvm.org/D51610 Reviewer: rampitec llvm-svn: 341636
2018-09-07 17:05:34 +08:00
---
name: smrd_vgpr_offset_imm
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
%4:vgpr_32 = COPY $vgpr0
%3:sgpr_32 = COPY $sgpr3
%2:sgpr_32 = COPY $sgpr2
%1:sgpr_32 = COPY $sgpr1
%0:sgpr_32 = COPY $sgpr0
%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%6:sreg_32_xm0 = S_MOV_B32 4095
%8:vgpr_32 = COPY %6
AMDGPU: Rename add/sub with carry out instructions The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
2020-07-14 21:18:36 +08:00
%7:vgpr_32 = V_ADD_CO_U32_e32 %4, killed %8, implicit-def dead $vcc, implicit $exec
[AMDGPU] Preliminary patch for divergence driven instruction selection. Fold immediate SMRD offset. Differential revision: https://reviews.llvm.org/D51610 Reviewer: rampitec llvm-svn: 341636
2018-09-07 17:05:34 +08:00
%10:sreg_32 = COPY %7
[AMDGPU] gfx1010 VMEM and SMEM implementation Differential Revision: https://reviews.llvm.org/D61330 llvm-svn: 359621
2019-05-01 06:08:23 +08:00
%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0, 0
[AMDGPU] Preliminary patch for divergence driven instruction selection. Fold immediate SMRD offset. Differential revision: https://reviews.llvm.org/D51610 Reviewer: rampitec llvm-svn: 341636
2018-09-07 17:05:34 +08:00
$vgpr0 = COPY %9
SI_RETURN_TO_EPILOG $vgpr0
...
[AMDGPU] Preliminary patch for divergence driven instruction selection. Load offset inlining pattern changed. Differential revision: https://reviews.llvm.org/D51975 Reviewers: rampitec llvm-svn: 342115
2018-09-13 14:34:56 +08:00
AMDGPU: Divergence-driven selection of scalar buffer load intrinsics Summary: Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if the load is really uniform. So select the scalar load intrinsics directly to either VMEM or SMRD buffer loads based on divergence analysis. If an offset happens to end up in a VGPR -- either because a floating point calculation was involved, or due to other remaining deficiencies in SIFixSGPRCopies -- we use v_readfirstlane. There is some unrelated churn in tests since we now select MUBUF offsets in a unified way with non-scalar buffer loads. Change-Id: I170e6816323beb1348677b358c9d380865cd1a19 Reviewers: arsenm, alex-t, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53283 llvm-svn: 348050
2018-12-01 06:55:38 +08:00
# GCN-LABEL: name: smrd_vgpr_offset_imm_add_u32
# GCN: V_READFIRSTLANE_B32
# GCN: S_BUFFER_LOAD_DWORD_SGPR
[AMDGPU] Preliminary patch for divergence driven instruction selection. Load offset inlining pattern changed. Differential revision: https://reviews.llvm.org/D51975 Reviewers: rampitec llvm-svn: 342115
2018-09-13 14:34:56 +08:00
---
name: smrd_vgpr_offset_imm_add_u32
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
%4:vgpr_32 = COPY $vgpr0
%3:sgpr_32 = COPY $sgpr3
%2:sgpr_32 = COPY $sgpr2
%1:sgpr_32 = COPY $sgpr1
%0:sgpr_32 = COPY $sgpr0
%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%6:sreg_32_xm0 = S_MOV_B32 4095
%8:vgpr_32 = COPY %6
%7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec
%10:sreg_32 = COPY %7
[AMDGPU] gfx1010 VMEM and SMEM implementation Differential Revision: https://reviews.llvm.org/D61330 llvm-svn: 359621
2019-05-01 06:08:23 +08:00
%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0, 0 :: (dereferenceable invariant load 4)
[AMDGPU] Preliminary patch for divergence driven instruction selection. Load offset inlining pattern changed. Differential revision: https://reviews.llvm.org/D51975 Reviewers: rampitec llvm-svn: 342115
2018-09-13 14:34:56 +08:00
$vgpr0 = COPY %9
SI_RETURN_TO_EPILOG $vgpr0
...