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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo...

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AMDGPU/GlobalISel: Try generated matcher with intrinsics llvm-svn: 364933
2019-07-02 22:52:16 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# FIXME: Need to deal with constant bus restriction
# ---
# name: mbcnt_lo_ss
# legalized: true
# regBankSelected: true
# body: |
# bb.0:
# liveins: $sgpr0, $sgpr1
# %0:sgpr(s32) = COPY $sgpr0
# %1:sgpr(s32) = COPY $sgpr1
# %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
# S_ENDPGM 0, implicit %2
# ...
---
name: mbcnt_lo_sv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: mbcnt_lo_sv
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Try generated matcher with intrinsics llvm-svn: 364933
2019-07-02 22:52:16 +08:00
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: smin_s32_vs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: smin_s32_vs
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Try generated matcher with intrinsics llvm-svn: 364933
2019-07-02 22:52:16 +08:00
; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: smin_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: smin_s32_vv
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
S_ENDPGM 0, implicit %2
...