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llvm-project/llvm/test/CodeGen/RISCV/musttail-call.ll

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[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
; Check that we error out if tail is not possible but call is marked as mustail.
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
2020-02-12 15:01:35 +08:00
; RUN: not --crash llc -mtriple riscv32-unknown-linux-gnu -o - %s \
[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
; RUN: 2>&1 | FileCheck %s
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
2020-02-12 15:01:35 +08:00
; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
; RUN: 2>&1 | FileCheck %s
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
2020-02-12 15:01:35 +08:00
; RUN: not --crash llc -mtriple riscv64-unknown-linux-gnu -o - %s \
[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
; RUN: 2>&1 | FileCheck %s
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
2020-02-12 15:01:35 +08:00
; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
; RUN: 2>&1 | FileCheck %s
%struct.A = type { i32 }
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
declare void @callee_musttail(%struct.A* sret(%struct.A) %a)
define void @caller_musttail(%struct.A* sret(%struct.A) %a) {
[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
; CHECK: LLVM ERROR: failed to perform tail call elimination on a call site marked musttail
entry:
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
musttail call void @callee_musttail(%struct.A* sret(%struct.A) %a)
[RISCV] Lower the tail pseudoinstruction This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
2018-05-24 06:44:08 +08:00
ret void
}