2017-08-02 07:14:32 +08:00
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//===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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2018-05-01 23:54:18 +08:00
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/// This pass removes redundant S_OR_B64 instructions enabling lanes in
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2017-08-02 07:14:32 +08:00
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/// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
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/// vector instructions between them we can only keep outer SI_END_CF, given
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/// that CFG is structured and exec bits of the outer end statement are always
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/// not less than exec bit of the inner one.
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///
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/// This needs to be done before the RA to eliminate saved exec bits registers
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/// but after register coalescer to have no vector registers copies in between
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/// of different end cf statements.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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2017-12-13 10:51:04 +08:00
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#include "llvm/CodeGen/LiveIntervals.h"
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2017-08-02 07:14:32 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
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namespace {
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class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
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initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "SI optimize exec mask operations pre-RA";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
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"SI optimize exec mask operations pre-RA", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
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"SI optimize exec mask operations pre-RA", false, false)
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char SIOptimizeExecMaskingPreRA::ID = 0;
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char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
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FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
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return new SIOptimizeExecMaskingPreRA();
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}
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static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
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return MI.getOpcode() == AMDGPU::S_OR_B64 &&
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MI.modifiesRegister(AMDGPU::EXEC, TRI);
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}
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static bool isFullExecCopy(const MachineInstr& MI) {
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return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
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}
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static unsigned getOrNonExecReg(const MachineInstr &MI,
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const SIInstrInfo &TII) {
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auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
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if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
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return Op->getReg();
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Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
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if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
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return Op->getReg();
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return AMDGPU::NoRegister;
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}
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static MachineInstr* getOrExecSource(const MachineInstr &MI,
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const SIInstrInfo &TII,
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const MachineRegisterInfo &MRI) {
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auto SavedExec = getOrNonExecReg(MI, TII);
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if (SavedExec == AMDGPU::NoRegister)
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return nullptr;
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auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);
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if (!SaveExecInst || !isFullExecCopy(*SaveExecInst))
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return nullptr;
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return SaveExecInst;
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}
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bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
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2017-12-16 06:22:58 +08:00
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if (skipFunction(MF.getFunction()))
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2017-08-02 07:14:32 +08:00
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return false;
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const SIInstrInfo *TII = ST.getInstrInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
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2017-08-16 12:43:49 +08:00
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DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
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2017-08-02 07:14:32 +08:00
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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2017-08-16 12:43:49 +08:00
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// Try to remove unneeded instructions before s_endpgm.
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if (MBB.succ_empty()) {
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if (MBB.empty() || MBB.back().getOpcode() != AMDGPU::S_ENDPGM)
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continue;
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SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
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while (!Blocks.empty()) {
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auto CurBB = Blocks.pop_back_val();
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auto I = CurBB->rbegin(), E = CurBB->rend();
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if (I != E) {
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if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
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++I;
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else if (I->isBranch())
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continue;
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}
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while (I != E) {
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2018-05-09 10:42:00 +08:00
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if (I->isDebugInstr()) {
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2017-12-06 02:23:17 +08:00
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I = std::next(I);
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2017-08-16 12:43:49 +08:00
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continue;
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2017-12-06 02:23:17 +08:00
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}
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2017-08-16 12:43:49 +08:00
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if (I->mayStore() || I->isBarrier() || I->isCall() ||
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I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
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break;
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DEBUG(dbgs() << "Removing no effect instruction: " << *I << '\n');
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2017-09-09 02:51:26 +08:00
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for (auto &Op : I->operands()) {
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2017-08-16 12:43:49 +08:00
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if (Op.isReg())
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RecalcRegs.insert(Op.getReg());
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2017-09-09 02:51:26 +08:00
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}
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2017-08-16 12:43:49 +08:00
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auto Next = std::next(I);
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LIS->RemoveMachineInstrFromMaps(*I);
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I->eraseFromParent();
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I = Next;
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Changed = true;
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}
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if (I != E)
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continue;
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// Try to ascend predecessors.
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for (auto *Pred : CurBB->predecessors()) {
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if (Pred->succ_size() == 1)
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Blocks.push_back(Pred);
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}
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}
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continue;
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}
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// Try to collapse adjacent endifs.
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2017-08-02 07:14:32 +08:00
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auto Lead = MBB.begin(), E = MBB.end();
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if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI))
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continue;
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const MachineBasicBlock* Succ = *MBB.succ_begin();
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if (!MBB.isLayoutSuccessor(Succ))
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continue;
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auto I = std::next(Lead);
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for ( ; I != E; ++I)
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if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))
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break;
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if (I != E)
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continue;
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const auto NextLead = Succ->begin();
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if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) ||
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!getOrExecSource(*NextLead, *TII, MRI))
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continue;
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DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
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2017-08-02 09:18:57 +08:00
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auto SaveExec = getOrExecSource(*Lead, *TII, MRI);
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2017-08-02 07:14:32 +08:00
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unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII);
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2017-09-09 02:51:26 +08:00
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for (auto &Op : Lead->operands()) {
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if (Op.isReg())
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RecalcRegs.insert(Op.getReg());
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}
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2017-08-02 07:14:32 +08:00
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LIS->RemoveMachineInstrFromMaps(*Lead);
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Lead->eraseFromParent();
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if (SaveExecReg) {
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LIS->removeInterval(SaveExecReg);
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LIS->createAndComputeVirtRegInterval(SaveExecReg);
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}
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Changed = true;
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2017-08-02 07:44:35 +08:00
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// If the only use of saved exec in the removed instruction is S_AND_B64
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// fold the copy now.
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if (!SaveExec || !SaveExec->isFullCopy())
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continue;
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unsigned SavedExec = SaveExec->getOperand(0).getReg();
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bool SafeToReplace = true;
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for (auto& U : MRI.use_nodbg_instructions(SavedExec)) {
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if (U.getParent() != SaveExec->getParent()) {
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SafeToReplace = false;
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break;
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}
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DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n');
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}
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if (SafeToReplace) {
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LIS->RemoveMachineInstrFromMaps(*SaveExec);
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SaveExec->eraseFromParent();
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MRI.replaceRegWith(SavedExec, AMDGPU::EXEC);
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LIS->removeInterval(SavedExec);
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}
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2017-08-02 07:14:32 +08:00
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}
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if (Changed) {
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2017-08-16 12:43:49 +08:00
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for (auto Reg : RecalcRegs) {
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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LIS->removeInterval(Reg);
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if (!MRI.reg_empty(Reg))
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LIS->createAndComputeVirtRegInterval(Reg);
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} else {
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for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U)
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LIS->removeRegUnit(*U);
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}
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}
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2017-08-02 07:14:32 +08:00
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}
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return Changed;
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}
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