forked from OSchip/llvm-project
26 lines
679 B
TableGen
26 lines
679 B
TableGen
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//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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include "ARCRegisterInfo.td"
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include "ARCInstrInfo.td"
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include "ARCCallingConv.td"
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def ARCInstrInfo : InstrInfo;
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def ARC : Target {
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let InstructionSet = ARCInstrInfo;
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}
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