2012-05-11 04:24:28 +08:00
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def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
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SDTCisVT<0, f32>,
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SDTCisPtrTy<1>]>;
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def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
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let isReMaterializable = 1, isMoveImm = 1 in
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def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
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"$dst = CONST32(#$global)",
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[(set (f32 IntRegs:$dst),
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(HexagonFCONST32 tglobaladdr:$global))]>,
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Requires<[HasV5T]>;
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let isReMaterializable = 1, isMoveImm = 1 in
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def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
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"$dst = CONST64(#$src1)",
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[(set DoubleRegs:$dst, fpimm:$src1)]>,
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Requires<[HasV5T]>;
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let isReMaterializable = 1, isMoveImm = 1 in
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def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
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"$dst = CONST32(#$src1)",
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[(set IntRegs:$dst, fpimm:$src1)]>,
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Requires<[HasV5T]>;
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// Transfer immediate float.
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// Only works with single precision fp value.
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// For double precision, use CONST64_float_real, as 64bit transfer
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// can only hold 40-bit values - 32 from const ext + 8 bit immediate.
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2013-05-11 04:27:34 +08:00
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// Make sure that complexity is more than the CONST32 pattern in
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// HexagonInstrInfo.td patterns.
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let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
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isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
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isCodeGenOnly = 1 in
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def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
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"$dst = #$src1",
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2012-05-11 04:24:28 +08:00
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[(set IntRegs:$dst, fpimm:$src1)]>,
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Requires<[HasV5T]>;
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2013-05-11 04:27:34 +08:00
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let isExtended = 1, opExtendable = 2, isPredicated = 1,
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neverHasSideEffects = 1, validSubTargets = HasV5SubT in
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2012-05-11 04:24:28 +08:00
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def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
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2013-05-11 04:27:34 +08:00
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(ins PredRegs:$src1, f32Ext:$src2),
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"if ($src1) $dst = #$src2",
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2012-05-11 04:24:28 +08:00
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[]>,
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Requires<[HasV5T]>;
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2013-05-11 04:27:34 +08:00
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let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
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neverHasSideEffects = 1, validSubTargets = HasV5SubT in
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2012-05-11 04:24:28 +08:00
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def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
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2013-05-11 04:27:34 +08:00
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(ins PredRegs:$src1, f32Ext:$src2),
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"if (!$src1) $dst =#$src2",
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2012-05-11 04:24:28 +08:00
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[]>,
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Requires<[HasV5T]>;
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// Convert single precision to double precision and vice-versa.
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def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
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"$dst = convert_sf2df($src)",
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[(set DoubleRegs:$dst, (fextend IntRegs:$src))]>,
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Requires<[HasV5T]>;
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def CONVERT_df2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
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"$dst = convert_df2sf($src)",
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[(set IntRegs:$dst, (fround DoubleRegs:$src))]>,
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Requires<[HasV5T]>;
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// Load.
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def LDrid_f : LDInst<(outs DoubleRegs:$dst),
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(ins MEMri:$addr),
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"$dst = memd($addr)",
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[(set DoubleRegs:$dst, (f64 (load ADDRriS11_3:$addr)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 20 in
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def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
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2012-05-15 03:35:42 +08:00
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(ins IntRegs:$src1, s11_3Imm:$offset),
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2012-05-11 04:24:28 +08:00
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"$dst = memd($src1+#$offset)",
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[(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1,
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2012-05-15 03:35:42 +08:00
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s11_3ImmPred:$offset))))]>,
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2012-05-11 04:24:28 +08:00
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Requires<[HasV5T]>;
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def LDriw_f : LDInst<(outs IntRegs:$dst),
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(ins MEMri:$addr), "$dst = memw($addr)",
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[(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 20 in
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def LDriw_indexed_f : LDInst<(outs IntRegs:$dst),
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2012-05-15 03:35:42 +08:00
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(ins IntRegs:$src1, s11_2Imm:$offset),
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2012-05-11 04:24:28 +08:00
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"$dst = memw($src1+#$offset)",
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[(set IntRegs:$dst, (f32 (load (add IntRegs:$src1,
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2012-05-15 03:35:42 +08:00
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s11_2ImmPred:$offset))))]>,
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2012-05-11 04:24:28 +08:00
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Requires<[HasV5T]>;
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// Store.
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def STriw_f : STInst<(outs),
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(ins MEMri:$addr, IntRegs:$src1),
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"memw($addr) = $src1",
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[(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 10 in
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def STriw_indexed_f : STInst<(outs),
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2012-05-15 03:35:42 +08:00
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(ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
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2012-05-11 04:24:28 +08:00
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"memw($src1+#$src2) = $src3",
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[(store (f32 IntRegs:$src3),
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2012-05-15 03:35:42 +08:00
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(add IntRegs:$src1, s11_2ImmPred:$src2))]>,
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2012-05-11 04:24:28 +08:00
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Requires<[HasV5T]>;
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def STrid_f : STInst<(outs),
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(ins MEMri:$addr, DoubleRegs:$src1),
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"memd($addr) = $src1",
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[(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>,
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Requires<[HasV5T]>;
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// Indexed store double word.
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let AddedComplexity = 10 in
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def STrid_indexed_f : STInst<(outs),
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2012-05-15 03:35:42 +08:00
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(ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
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2012-05-11 04:24:28 +08:00
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"memd($src1+#$src2) = $src3",
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[(store (f64 DoubleRegs:$src3),
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2012-05-15 03:35:42 +08:00
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(add IntRegs:$src1, s11_3ImmPred:$src2))]>,
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2012-05-11 04:24:28 +08:00
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Requires<[HasV5T]>;
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// Add
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let isCommutable = 1 in
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def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = sfadd($src1, $src2)",
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[(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>,
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Requires<[HasV5T]>;
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let isCommutable = 1 in
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def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = dfadd($src1, $src2)",
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[(set DoubleRegs:$dst, (fadd DoubleRegs:$src1,
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DoubleRegs:$src2))]>,
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Requires<[HasV5T]>;
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def fSUB_rr : ALU64_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = sfsub($src1, $src2)",
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[(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
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Requires<[HasV5T]>;
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def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = dfsub($src1, $src2)",
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[(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
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DoubleRegs:$src2))]>,
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Requires<[HasV5T]>;
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let isCommutable = 1 in
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def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = sfmpy($src1, $src2)",
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[(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
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Requires<[HasV5T]>;
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let isCommutable = 1 in
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def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = dfmpy($src1, $src2)",
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[(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
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DoubleRegs:$src2))]>,
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Requires<[HasV5T]>;
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// Compare.
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let isCompare = 1 in {
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multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
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def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set PredRegs:$dst,
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(OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
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Requires<[HasV5T]>;
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}
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multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
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def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set PredRegs:$dst,
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(OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
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Requires<[HasV5T]>;
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}
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}
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defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
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defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
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defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
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defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
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defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
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defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
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defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
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defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
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defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
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defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
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defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
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defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
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// olt.
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def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
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(f64 DoubleRegs:$src1)))>,
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Requires<[HasV5T]>;
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// gt.
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def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
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(f64 (CONST64_Float_Real fpimm:$src2))))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
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Requires<[HasV5T]>;
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// ult.
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def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
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(f64 DoubleRegs:$src1)))>,
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Requires<[HasV5T]>;
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// le.
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// rs <= rt -> rt >= rs.
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def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
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|
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|
|
|
|
|
|
|
|
|
|
// Rss <= Rtt -> Rtt >= Rss.
|
|
|
|
|
def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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|
|
|
|
(i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
|
|
|
|
(i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
|
|
|
|
|
DoubleRegs:$src1))>,
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|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
// rs <= rt -> rt >= rs.
|
|
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|
|
def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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|
|
|
|
(i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
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|
|
|
|
(i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
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|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
// Rss <= Rtt -> Rtt >= Rss.
|
|
|
|
|
def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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|
|
|
|
(i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
|
|
|
|
(i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
|
|
|
|
|
DoubleRegs:$src1))>,
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|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
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|
|
|
|
// ne.
|
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|
|
def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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|
|
|
(i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1,
|
|
|
|
|
(f64 (CONST64_Float_Real fpimm:$src2)))))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
|
|
|
|
(i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1,
|
|
|
|
|
(f64 (CONST64_Float_Real fpimm:$src2)))))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
// Convert Integer to Floating Point.
|
|
|
|
|
def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_d2sf($src)",
|
|
|
|
|
[(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_ud2sf($src)",
|
|
|
|
|
[(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_uw2sf($src)",
|
|
|
|
|
[(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_w2sf($src)",
|
|
|
|
|
[(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_d2df($src)",
|
|
|
|
|
[(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_ud2df($src)",
|
|
|
|
|
[(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_uw2df($src)",
|
|
|
|
|
[(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_w2df($src)",
|
|
|
|
|
[(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
// Convert Floating Point to Integer - default.
|
|
|
|
|
def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2uw($src):chop",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2w($src):chop",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2uw($src):chop",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2w($src):chop",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2d($src):chop",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2ud($src):chop",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2d($src):chop",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2ud($src):chop",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
// Convert Floating Point to Integer: non-chopped.
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2uw($src)",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2w($src)",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2uw($src)",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2w($src)",
|
|
|
|
|
[(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2d($src)",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
|
|
|
|
|
"$dst = convert_df2ud($src)",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2d($src)",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 20 in
|
|
|
|
|
def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
|
|
|
|
|
"$dst = convert_sf2ud($src)",
|
|
|
|
|
[(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
|
|
|
|
|
Requires<[HasV5T, IEEERndNearV5T]>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
|
|
|
|
|
def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
|
|
|
|
|
(i32 (TFR IntRegs:$src))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
|
|
|
|
|
(f32 (TFR IntRegs:$src))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
|
|
|
|
|
(i64 (TFR64 DoubleRegs:$src))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
|
|
|
|
|
(f64 (TFR64 DoubleRegs:$src))>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
// Floating point fused multiply-add.
|
|
|
|
|
def FMADD_dp : ALU64_acc<(outs DoubleRegs:$dst),
|
|
|
|
|
(ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
|
|
|
|
"$dst += dfmpy($src2, $src3)",
|
|
|
|
|
[(set (f64 DoubleRegs:$dst),
|
|
|
|
|
(fma DoubleRegs:$src2, DoubleRegs:$src3, DoubleRegs:$src1))],
|
|
|
|
|
"$src1 = $dst">,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
|
|
|
|
|
(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
|
|
|
|
"$dst += sfmpy($src2, $src3)",
|
|
|
|
|
[(set (f32 IntRegs:$dst),
|
|
|
|
|
(fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))],
|
|
|
|
|
"$src1 = $dst">,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Floating point max/min.
|
|
|
|
|
let AddedComplexity = 100 in
|
|
|
|
|
def FMAX_dp : ALU64_rr<(outs DoubleRegs:$dst),
|
|
|
|
|
(ins DoubleRegs:$src1, DoubleRegs:$src2),
|
|
|
|
|
"$dst = dfmax($src1, $src2)",
|
|
|
|
|
[(set DoubleRegs:$dst, (f64 (select (i1 (setolt DoubleRegs:$src2,
|
|
|
|
|
DoubleRegs:$src1)),
|
|
|
|
|
DoubleRegs:$src1,
|
|
|
|
|
DoubleRegs:$src2)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 100 in
|
|
|
|
|
def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
|
|
|
|
|
(ins IntRegs:$src1, IntRegs:$src2),
|
|
|
|
|
"$dst = sfmax($src1, $src2)",
|
|
|
|
|
[(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2,
|
|
|
|
|
IntRegs:$src1)),
|
|
|
|
|
IntRegs:$src1,
|
|
|
|
|
IntRegs:$src2)))]>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
let AddedComplexity = 100 in
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def FMIN_dp : ALU64_rr<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, DoubleRegs:$src2),
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"$dst = dfmin($src1, $src2)",
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[(set DoubleRegs:$dst, (f64 (select (i1 (setogt DoubleRegs:$src2,
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DoubleRegs:$src1)),
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DoubleRegs:$src1,
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DoubleRegs:$src2)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 100 in
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def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = sfmin($src1, $src2)",
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[(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2,
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IntRegs:$src1)),
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IntRegs:$src1,
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IntRegs:$src2)))]>,
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Requires<[HasV5T]>;
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// Pseudo instruction to encode a set of conditional transfers.
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// This instruction is used instead of a mux and trades-off codesize
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// for performance. We conduct this transformation optimistically in
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// the hope that these instructions get promoted to dot-new transfers.
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let AddedComplexity = 100, isPredicated = 1 in
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def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
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IntRegs:$src2,
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IntRegs:$src3),
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"Error; should not emit",
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[(set IntRegs:$dst, (f32 (select PredRegs:$src1,
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IntRegs:$src2,
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IntRegs:$src3)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 100, isPredicated = 1 in
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def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
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DoubleRegs:$src2,
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DoubleRegs:$src3),
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"Error; should not emit",
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[(set DoubleRegs:$dst, (f64 (select PredRegs:$src1,
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DoubleRegs:$src2,
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DoubleRegs:$src3)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 100, isPredicated = 1 in
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def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3),
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"Error; should not emit",
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[(set IntRegs:$dst,
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(f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 100, isPredicated = 1 in
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def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3),
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"Error; should not emit",
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[(set IntRegs:$dst,
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(f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>,
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Requires<[HasV5T]>;
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let AddedComplexity = 100, isPredicated = 1 in
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def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, f32imm:$src2, f32imm:$src3),
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"Error; should not emit",
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[(set IntRegs:$dst, (f32 (select PredRegs:$src1,
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fpimm:$src2,
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fpimm:$src3)))]>,
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Requires<[HasV5T]>;
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def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(f32 IntRegs:$src3),
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(f32 IntRegs:$src4)),
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(TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
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IntRegs:$src3)>, Requires<[HasV5T]>;
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def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(f64 DoubleRegs:$src3),
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(f64 DoubleRegs:$src4)),
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(TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
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DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
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// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
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def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3),
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(TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>;
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// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
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|
// => r0 = TFR_condset_ri(p0, r1, #i)
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def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
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(TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
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// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
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|
// => r0 = TFR_condset_ir(p0, #i, r1)
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|
def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
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(TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
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|
def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
|
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|
|
|
(i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
|
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|
|
|
Requires<[HasV5T]>;
|
|
|
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|
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|
|
def : Pat <(fabs (f32 IntRegs:$src1)),
|
|
|
|
|
(CLRBIT_31 (f32 IntRegs:$src1), 31)>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
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|
|
def : Pat <(fneg (f32 IntRegs:$src1)),
|
|
|
|
|
(TOGBIT_31 (f32 IntRegs:$src1), 31)>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
def : Pat <(fabs (f64 DoubleRegs:$src1)),
|
|
|
|
|
(CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
|
|
|
|
|
def : Pat <(fabs (f64 DoubleRegs:$src1)),
|
|
|
|
|
(CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
|
|
|
|
|
Requires<[HasV5T]>;
|
|
|
|
|
*/
|
