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llvm-project/llvm/test/CodeGen/X86/sext-i1.ll

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Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=CHECK --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=CHECK --check-prefix=X64
Implement cond ? -1 : 0 with sbb. llvm-svn: 94490
2010-01-26 10:00:44 +08:00
; rdar://7573216
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs. This fixes PR6146. llvm-svn: 94731
2010-01-28 09:57:22 +08:00
; PR6146
Implement cond ? -1 : 0 with sbb. llvm-svn: 94490
2010-01-26 10:00:44 +08:00
define i32 @t1(i32 %x) nounwind readnone ssp {
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; X32-LABEL: t1:
; X32: # BB#0:
; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; X32-NEXT: sbbl %eax, %eax
; X32-NEXT: retl
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
;
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; X64-LABEL: t1:
; X64: # BB#0:
; X64-NEXT: cmpl $1, %edi
; X64-NEXT: sbbl %eax, %eax
; X64-NEXT: retq
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
%t0 = icmp eq i32 %x, 0
%if = select i1 %t0, i32 -1, i32 0
ret i32 %if
Implement cond ? -1 : 0 with sbb. llvm-svn: 94490
2010-01-26 10:00:44 +08:00
}
define i32 @t2(i32 %x) nounwind readnone ssp {
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; X32-LABEL: t2:
; X32: # BB#0:
; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; X32-NEXT: sbbl %eax, %eax
; X32-NEXT: retl
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
;
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; X64-LABEL: t2:
; X64: # BB#0:
; X64-NEXT: cmpl $1, %edi
; X64-NEXT: sbbl %eax, %eax
; X64-NEXT: retq
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
%t0 = icmp eq i32 %x, 0
%if = sext i1 %t0 to i32
ret i32 %if
Implement cond ? -1 : 0 with sbb. llvm-svn: 94490
2010-01-26 10:00:44 +08:00
}
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs. This fixes PR6146. llvm-svn: 94731
2010-01-28 09:57:22 +08:00
define i32 @t3() nounwind readonly {
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; X32-LABEL: t3:
; X32: # BB#0: # %entry
; X32-NEXT: cmpl $1, %eax
; X32-NEXT: sbbl %eax, %eax
; X32-NEXT: cmpl %eax, %eax
; X32-NEXT: sbbl %eax, %eax
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: retl
;
; X64-LABEL: t3:
; X64: # BB#0: # %entry
[x86] use more shift or LEA for select-of-constants (2nd try) The previous rev (r310208) failed to account for overflow when subtracting the constants to see if they're suitable for shift/lea. This version add a check for that and more test were added in r310490. We can convert any select-of-constants to math ops: http://rise4fun.com/Alive/d7d For this patch, I'm enhancing an existing x86 transform that uses fake multiplies (they always become shl/lea) to avoid cmov or branching. The current code misses cases where we have a negative constant and a positive constant, so this is just trying to plug that hole. The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start with a select in IR, create a select DAG node, convert it into a sext, convert it back into a select, and then lower it to sext machine code. Some notes about the test diffs: 1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR. 2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. We could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a post-DAG problem though. 3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if that's a regression, but those would always be nearly equivalent. 4. pr22338.ll and sext-i1.ll - These tests have undef operands, so we don't actually care about these diffs. 5. sbb.ll - This shows a win for what is likely a common case: choose -1 or 0. 6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again. 7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops. Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass. Differential Revision: https://reviews.llvm.org/D35340 llvm-svn: 310717
2017-08-11 23:44:14 +08:00
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: testl %eax, %eax
; X64-NEXT: sete %al
; X64-NEXT: negq %rax
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; X64-NEXT: cmpq %rax, %rax
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs. This fixes PR6146. llvm-svn: 94731
2010-01-28 09:57:22 +08:00
entry:
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
%not.tobool = icmp eq i32 undef, 0
%cond = sext i1 %not.tobool to i32
%conv = sext i1 %not.tobool to i64
%add13 = add i64 0, %conv
%cmp = icmp ult i64 undef, %add13
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs. This fixes PR6146. llvm-svn: 94731
2010-01-28 09:57:22 +08:00
br i1 %cmp, label %if.then, label %if.end
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
if.then:
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs. This fixes PR6146. llvm-svn: 94731
2010-01-28 09:57:22 +08:00
br label %if.end
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
if.end:
%xor27 = xor i32 undef, %cond
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs. This fixes PR6146. llvm-svn: 94731
2010-01-28 09:57:22 +08:00
ret i32 0
}
[DAGCombine] Remove SIGN_EXTEND-related inf-loop The patch's author points out that, despite the function's documentation, getSetCCResultType is only used to get the SETCC result type (with one here-removed problematic exception). In one case, getSetCCResultType was being used to get the predicate type to use for a SELECT node, and then SIGN_EXTENDing (or truncating) to get the input predicate to match that type. Unfortunately, this was happening inside visitSIGN_EXTEND, and creating new SIGN_EXTEND nodes was causing an infinite loop. In addition, this behavior was wrong if a target was not using ZeroOrNegativeOneBooleanContent. Lastly, the extension/truncation seems unnecessary here: SELECT is defined as: Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not i1 then the high bits must conform to getBooleanContents. So here we remove this use of getSetCCResultType and update getSetCCResultType's documentation to reflect its actual uses. Patch by deadal nix! llvm-svn: 219141
2014-10-07 04:19:47 +08:00
define i32 @t4(i64 %x) nounwind readnone ssp {
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; X32-LABEL: t4:
; X32: # BB#0:
[x86] use more shift or LEA for select-of-constants (2nd try) The previous rev (r310208) failed to account for overflow when subtracting the constants to see if they're suitable for shift/lea. This version add a check for that and more test were added in r310490. We can convert any select-of-constants to math ops: http://rise4fun.com/Alive/d7d For this patch, I'm enhancing an existing x86 transform that uses fake multiplies (they always become shl/lea) to avoid cmov or branching. The current code misses cases where we have a negative constant and a positive constant, so this is just trying to plug that hole. The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start with a select in IR, create a select DAG node, convert it into a sext, convert it back into a select, and then lower it to sext machine code. Some notes about the test diffs: 1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR. 2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. We could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a post-DAG problem though. 3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if that's a regression, but those would always be nearly equivalent. 4. pr22338.ll and sext-i1.ll - These tests have undef operands, so we don't actually care about these diffs. 5. sbb.ll - This shows a win for what is likely a common case: choose -1 or 0. 6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again. 7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops. Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass. Differential Revision: https://reviews.llvm.org/D35340 llvm-svn: 310717
2017-08-11 23:44:14 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; X32-NEXT: xorl %eax, %eax
[x86] use more shift or LEA for select-of-constants (2nd try) The previous rev (r310208) failed to account for overflow when subtracting the constants to see if they're suitable for shift/lea. This version add a check for that and more test were added in r310490. We can convert any select-of-constants to math ops: http://rise4fun.com/Alive/d7d For this patch, I'm enhancing an existing x86 transform that uses fake multiplies (they always become shl/lea) to avoid cmov or branching. The current code misses cases where we have a negative constant and a positive constant, so this is just trying to plug that hole. The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start with a select in IR, create a select DAG node, convert it into a sext, convert it back into a select, and then lower it to sext machine code. Some notes about the test diffs: 1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR. 2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. We could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a post-DAG problem though. 3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if that's a regression, but those would always be nearly equivalent. 4. pr22338.ll and sext-i1.ll - These tests have undef operands, so we don't actually care about these diffs. 5. sbb.ll - This shows a win for what is likely a common case: choose -1 or 0. 6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again. 7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops. Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass. Differential Revision: https://reviews.llvm.org/D35340 llvm-svn: 310717
2017-08-11 23:44:14 +08:00
; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: sete %al
; X32-NEXT: negl %eax
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; X32-NEXT: retl
;
; X64-LABEL: t4:
; X64: # BB#0:
; X64-NEXT: cmpq $1, %rdi
; X64-NEXT: sbbl %eax, %eax
; X64-NEXT: retq
%t0 = icmp eq i64 %x, 0
%t1 = sext i1 %t0 to i32
ret i32 %t1
[DAGCombine] Remove SIGN_EXTEND-related inf-loop The patch's author points out that, despite the function's documentation, getSetCCResultType is only used to get the SETCC result type (with one here-removed problematic exception). In one case, getSetCCResultType was being used to get the predicate type to use for a SELECT node, and then SIGN_EXTENDing (or truncating) to get the input predicate to match that type. Unfortunately, this was happening inside visitSIGN_EXTEND, and creating new SIGN_EXTEND nodes was causing an infinite loop. In addition, this behavior was wrong if a target was not using ZeroOrNegativeOneBooleanContent. Lastly, the extension/truncation seems unnecessary here: SELECT is defined as: Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not i1 then the high bits must conform to getBooleanContents. So here we remove this use of getSetCCResultType and update getSetCCResultType's documentation to reflect its actual uses. Patch by deadal nix! llvm-svn: 219141
2014-10-07 04:19:47 +08:00
}
define i64 @t5(i32 %x) nounwind readnone ssp {
[x86] regenerate checks llvm-svn: 281523
2016-09-15 03:42:03 +08:00
; X32-LABEL: t5:
; X32: # BB#0:
; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; X32-NEXT: sbbl %eax, %eax
; X32-NEXT: movl %eax, %edx
; X32-NEXT: retl
;
; X64-LABEL: t5:
; X64: # BB#0:
; X64-NEXT: cmpl $1, %edi
; X64-NEXT: sbbq %rax, %rax
; X64-NEXT: retq
%t0 = icmp eq i32 %x, 0
%t1 = sext i1 %t0 to i64
ret i64 %t1
[DAGCombine] Remove SIGN_EXTEND-related inf-loop The patch's author points out that, despite the function's documentation, getSetCCResultType is only used to get the SETCC result type (with one here-removed problematic exception). In one case, getSetCCResultType was being used to get the predicate type to use for a SELECT node, and then SIGN_EXTENDing (or truncating) to get the input predicate to match that type. Unfortunately, this was happening inside visitSIGN_EXTEND, and creating new SIGN_EXTEND nodes was causing an infinite loop. In addition, this behavior was wrong if a target was not using ZeroOrNegativeOneBooleanContent. Lastly, the extension/truncation seems unnecessary here: SELECT is defined as: Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not i1 then the high bits must conform to getBooleanContents. So here we remove this use of getSetCCResultType and update getSetCCResultType's documentation to reflect its actual uses. Patch by deadal nix! llvm-svn: 219141
2014-10-07 04:19:47 +08:00
}
[x86] remove stale comments from tests; NFC llvm-svn: 295569
2017-02-19 05:07:37 +08:00
; sext (xor Bool, -1) --> sub (zext Bool), 1
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
define i32 @select_0_or_1s(i1 %cond) {
; X32-LABEL: select_0_or_1s:
; X32: # BB#0:
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X32-NEXT: andl $1, %eax
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X32-NEXT: decl %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X32-NEXT: retl
;
; X64-LABEL: select_0_or_1s:
; X64: # BB#0:
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-NEXT: andl $1, %edi
; X64-NEXT: leal -1(%rdi), %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X64-NEXT: retq
%not = xor i1 %cond, 1
%sext = sext i1 %not to i32
ret i32 %sext
}
[x86] remove stale comments from tests; NFC llvm-svn: 295569
2017-02-19 05:07:37 +08:00
; sext (xor Bool, -1) --> sub (zext Bool), 1
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
define i32 @select_0_or_1s_zeroext(i1 zeroext %cond) {
; X32-LABEL: select_0_or_1s_zeroext:
; X32: # BB#0:
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: decl %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X32-NEXT: retl
;
; X64-LABEL: select_0_or_1s_zeroext:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X64-NEXT: decl %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X64-NEXT: retq
%not = xor i1 %cond, 1
%sext = sext i1 %not to i32
ret i32 %sext
}
[x86] remove stale comments from tests; NFC llvm-svn: 295569
2017-02-19 05:07:37 +08:00
; sext (xor Bool, -1) --> sub (zext Bool), 1
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
define i32 @select_0_or_1s_signext(i1 signext %cond) {
; X32-LABEL: select_0_or_1s_signext:
; X32: # BB#0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X32-NEXT: andb $1, %al
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X32-NEXT: movzbl %al, %eax
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X32-NEXT: decl %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X32-NEXT: retl
;
; X64-LABEL: select_0_or_1s_signext:
; X64: # BB#0:
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X64-NEXT: andb $1, %dil
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X64-NEXT: movzbl %dil, %eax
[x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1 This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
2017-02-19 05:03:28 +08:00
; X64-NEXT: decl %eax
[x86] add tests for sext (not bool); NFC llvm-svn: 295495
2017-02-18 05:10:40 +08:00
; X64-NEXT: retq
%not = xor i1 %cond, 1
%sext = sext i1 %not to i32
ret i32 %sext
}