2015-12-07 04:12:19 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2016-01-10 03:59:27 +08:00
|
|
|
; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=X32
|
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=X64
|
2011-08-17 10:29:19 +08:00
|
|
|
|
|
|
|
|
define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: A:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2017-04-07 06:33:25 +08:00
|
|
|
; X32-NEXT: movl (%eax), %ecx
|
|
|
|
|
; X32-NEXT: movl 4(%eax), %eax
|
|
|
|
|
; X32-NEXT: vmovd %ecx, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: A:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load i64, i64* %ptr, align 8
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
|
|
|
|
|
ret <4 x i64> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <4 x i64> @A2(i64* %ptr, i64* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: A2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: movl (%ecx), %edx
|
2017-04-07 06:33:25 +08:00
|
|
|
; X32-NEXT: movl 4(%ecx), %ecx
|
|
|
|
|
; X32-NEXT: movl %ecx, 4(%eax)
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: movl %edx, (%eax)
|
2017-04-07 06:33:25 +08:00
|
|
|
; X32-NEXT: vmovd %edx, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: A2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: movq (%rdi), %rax
|
|
|
|
|
; X64-NEXT: vmovq %rax, %xmm0
|
|
|
|
|
; X64-NEXT: movq %rax, (%rsi)
|
2017-01-31 13:18:29 +08:00
|
|
|
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load i64, i64* %ptr, align 8
|
|
|
|
|
store i64 %q, i64* %ptr2, align 8 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
|
|
|
|
|
ret <4 x i64> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: B:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: B:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load i32, i32* %ptr, align 4
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
|
|
|
|
|
ret <8 x i32> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <8 x i32> @B2(i32* %ptr) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: B2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: B2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load i32, i32* %ptr, align 4
|
|
|
|
|
%vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
|
|
|
|
|
%vecinit8.i = insertelement <8 x i32> %vecinit6.i, i32 %q, i32 4
|
|
|
|
|
%vecinit10.i = insertelement <8 x i32> %vecinit8.i, i32 %q, i32 5
|
|
|
|
|
%vecinit12.i = insertelement <8 x i32> %vecinit10.i, i32 %q, i32 6
|
|
|
|
|
%vecinit14.i = insertelement <8 x i32> %vecinit12.i, i32 %q, i32 7
|
|
|
|
|
ret <8 x i32> %vecinit14.i
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i32> @B3(i32* %ptr, i32* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: B3:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: movl (%ecx), %ecx
|
|
|
|
|
; X32-NEXT: vmovd %ecx, %xmm0
|
|
|
|
|
; X32-NEXT: movl %ecx, (%eax)
|
2017-01-31 13:18:29 +08:00
|
|
|
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: B3:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: movl (%rdi), %eax
|
|
|
|
|
; X64-NEXT: vmovd %eax, %xmm0
|
|
|
|
|
; X64-NEXT: movl %eax, (%rsi)
|
2017-01-31 13:18:29 +08:00
|
|
|
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load i32, i32* %ptr, align 4
|
|
|
|
|
store i32 %q, i32* %ptr2, align 4 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
|
|
|
|
|
%vecinit8.i = insertelement <8 x i32> %vecinit6.i, i32 %q, i32 4
|
|
|
|
|
%vecinit10.i = insertelement <8 x i32> %vecinit8.i, i32 %q, i32 5
|
|
|
|
|
%vecinit12.i = insertelement <8 x i32> %vecinit10.i, i32 %q, i32 6
|
|
|
|
|
%vecinit14.i = insertelement <8 x i32> %vecinit12.i, i32 %q, i32 7
|
|
|
|
|
ret <8 x i32> %vecinit14.i
|
|
|
|
|
}
|
|
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: C:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastsd (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: C:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load double, double* %ptr, align 8
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
|
|
|
|
|
ret <4 x double> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <4 x double> @C2(double* %ptr, double* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: C2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; X32-NEXT: vmovsd %xmm0, (%eax)
|
2017-01-31 13:18:29 +08:00
|
|
|
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: C2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; X64-NEXT: vmovsd %xmm0, (%rsi)
|
2017-01-31 13:18:29 +08:00
|
|
|
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load double, double* %ptr, align 8
|
|
|
|
|
store double %q, double* %ptr2, align 8 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
|
|
|
|
|
ret <4 x double> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: D:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: D:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load float, float* %ptr, align 4
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <8 x float> undef, float %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
|
|
|
|
|
ret <8 x float> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <8 x float> @D2(float* %ptr) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: D2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: D2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load float, float* %ptr, align 4
|
|
|
|
|
%vecinit.i = insertelement <8 x float> undef, float %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
|
|
|
|
|
%vecinit8.i = insertelement <8 x float> %vecinit6.i, float %q, i32 4
|
|
|
|
|
%vecinit10.i = insertelement <8 x float> %vecinit8.i, float %q, i32 5
|
|
|
|
|
%vecinit12.i = insertelement <8 x float> %vecinit10.i, float %q, i32 6
|
|
|
|
|
%vecinit14.i = insertelement <8 x float> %vecinit12.i, float %q, i32 7
|
|
|
|
|
ret <8 x float> %vecinit14.i
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x float> @D3(float* %ptr, float* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: D3:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
2017-01-31 13:18:29 +08:00
|
|
|
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; X32-NEXT: vmovss %xmm0, (%eax)
|
|
|
|
|
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: D3:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2017-01-31 13:18:29 +08:00
|
|
|
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; X64-NEXT: vmovss %xmm0, (%rsi)
|
|
|
|
|
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load float, float* %ptr, align 4
|
|
|
|
|
store float %q, float* %ptr2, align 4 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <8 x float> undef, float %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
|
|
|
|
|
%vecinit8.i = insertelement <8 x float> %vecinit6.i, float %q, i32 4
|
|
|
|
|
%vecinit10.i = insertelement <8 x float> %vecinit8.i, float %q, i32 5
|
|
|
|
|
%vecinit12.i = insertelement <8 x float> %vecinit10.i, float %q, i32 6
|
|
|
|
|
%vecinit14.i = insertelement <8 x float> %vecinit12.i, float %q, i32 7
|
|
|
|
|
ret <8 x float> %vecinit14.i
|
|
|
|
|
}
|
|
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
;;;; 128-bit versions
|
|
|
|
|
|
2012-04-08 20:54:54 +08:00
|
|
|
define <4 x float> @e(float* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: e:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %xmm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: e:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %xmm0
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load float, float* %ptr, align 4
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
|
|
|
|
|
ret <4 x float> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <4 x float> @e2(float* %ptr, float* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: e2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
2017-01-31 13:18:29 +08:00
|
|
|
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; X32-NEXT: vmovss %xmm0, (%eax)
|
|
|
|
|
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: e2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2017-01-31 13:18:29 +08:00
|
|
|
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; X64-NEXT: vmovss %xmm0, (%rsi)
|
|
|
|
|
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
2017-01-31 13:18:27 +08:00
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load float, float* %ptr, align 4
|
|
|
|
|
store float %q, float* %ptr2, align 4 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
|
|
|
|
|
ret <4 x float> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-07 04:12:19 +08:00
|
|
|
; Don't broadcast constants on pre-AVX2 hardware.
|
2012-04-08 20:54:54 +08:00
|
|
|
define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: _e2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: vmovaps {{.*#+}} xmm0 = [-7.812500e-03,-7.812500e-03,-7.812500e-03,-7.812500e-03]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: _e2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vmovaps {{.*#+}} xmm0 = [-7.812500e-03,-7.812500e-03,-7.812500e-03,-7.812500e-03]
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 04:12:19 +08:00
|
|
|
entry:
|
|
|
|
|
%vecinit.i = insertelement <4 x float> undef, float 0xbf80000000000000, i32 0
|
2012-04-08 20:54:54 +08:00
|
|
|
%vecinit2.i = insertelement <4 x float> %vecinit.i, float 0xbf80000000000000, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3
|
|
|
|
|
ret <4 x float> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
define <4 x i32> @F(i32* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: F:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %xmm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: F:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %xmm0
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load i32, i32* %ptr, align 4
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %q, i32 3
|
|
|
|
|
ret <4 x i32> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <4 x i32> @F2(i32* %ptr, i32* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: F2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: movl (%ecx), %ecx
|
|
|
|
|
; X32-NEXT: movl %ecx, (%eax)
|
|
|
|
|
; X32-NEXT: vmovd %ecx, %xmm0
|
|
|
|
|
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: F2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: movl (%rdi), %eax
|
|
|
|
|
; X64-NEXT: movl %eax, (%rsi)
|
|
|
|
|
; X64-NEXT: vmovd %eax, %xmm0
|
|
|
|
|
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load i32, i32* %ptr, align 4
|
|
|
|
|
store i32 %q, i32* %ptr2, align 4 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %q, i32 3
|
|
|
|
|
ret <4 x i32> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-07 17:09:54 +08:00
|
|
|
; FIXME: Pointer adjusted broadcasts
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @load_splat_4i32_4i32_1111(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_4i32_4i32_1111:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vpshufd {{.*#+}} xmm0 = mem[1,1,1,1]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_4i32_4i32_1111:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vpshufd {{.*#+}} xmm0 = mem[1,1,1,1]
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <4 x i32>, <4 x i32>* %ptr
|
|
|
|
|
%ret = shufflevector <4 x i32> %ld, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
|
|
|
ret <4 x i32> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i32> @load_splat_8i32_4i32_33333333(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_8i32_4i32_33333333:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2016-06-28 21:24:05 +08:00
|
|
|
; X32-NEXT: vbroadcastss 12(%eax), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_8i32_4i32_33333333:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2016-06-28 21:24:05 +08:00
|
|
|
; X64-NEXT: vbroadcastss 12(%rdi), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <4 x i32>, <4 x i32>* %ptr
|
|
|
|
|
%ret = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
|
|
|
|
|
ret <8 x i32> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i32> @load_splat_8i32_8i32_55555555(<8 x i32>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_8i32_8i32_55555555:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2016-01-10 04:59:39 +08:00
|
|
|
; X32-NEXT: vbroadcastss 20(%eax), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_8i32_8i32_55555555:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2016-01-10 04:59:39 +08:00
|
|
|
; X64-NEXT: vbroadcastss 20(%rdi), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <8 x i32>, <8 x i32>* %ptr
|
|
|
|
|
%ret = shufflevector <8 x i32> %ld, <8 x i32> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
|
|
|
|
|
ret <8 x i32> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x float> @load_splat_4f32_4f32_1111(<4 x float>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_4f32_4f32_1111:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss 4(%eax), %xmm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_4f32_4f32_1111:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss 4(%rdi), %xmm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <4 x float>, <4 x float>* %ptr
|
|
|
|
|
%ret = shufflevector <4 x float> %ld, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
|
|
|
ret <4 x float> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x float> @load_splat_8f32_4f32_33333333(<4 x float>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_8f32_4f32_33333333:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss 12(%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_8f32_4f32_33333333:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss 12(%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <4 x float>, <4 x float>* %ptr
|
|
|
|
|
%ret = shufflevector <4 x float> %ld, <4 x float> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
|
|
|
|
|
ret <8 x float> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x float> @load_splat_8f32_8f32_55555555(<8 x float>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_8f32_8f32_55555555:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss 20(%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_8f32_8f32_55555555:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss 20(%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <8 x float>, <8 x float>* %ptr
|
|
|
|
|
%ret = shufflevector <8 x float> %ld, <8 x float> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
|
|
|
|
|
ret <8 x float> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @load_splat_2i64_2i64_1111(<2 x i64>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_2i64_2i64_1111:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_2i64_2i64_1111:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <2 x i64>, <2 x i64>* %ptr
|
|
|
|
|
%ret = shufflevector <2 x i64> %ld, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
|
|
|
|
|
ret <2 x i64> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i64> @load_splat_4i64_2i64_1111(<2 x i64>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_4i64_2i64_1111:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2016-06-28 21:24:05 +08:00
|
|
|
; X32-NEXT: vbroadcastsd 8(%eax), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_4i64_2i64_1111:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2016-06-28 21:24:05 +08:00
|
|
|
; X64-NEXT: vbroadcastsd 8(%rdi), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <2 x i64>, <2 x i64>* %ptr
|
|
|
|
|
%ret = shufflevector <2 x i64> %ld, <2 x i64> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
|
|
|
ret <4 x i64> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i64> @load_splat_4i64_4i64_2222(<4 x i64>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_4i64_4i64_2222:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2016-01-10 04:59:39 +08:00
|
|
|
; X32-NEXT: vbroadcastsd 16(%eax), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_4i64_4i64_2222:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2016-01-10 04:59:39 +08:00
|
|
|
; X64-NEXT: vbroadcastsd 16(%rdi), %ymm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <4 x i64>, <4 x i64>* %ptr
|
|
|
|
|
%ret = shufflevector <4 x i64> %ld, <4 x i64> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
|
|
|
|
|
ret <4 x i64> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x double> @load_splat_2f64_2f64_1111(<2 x double>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_2f64_2f64_1111:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2016-03-02 19:43:05 +08:00
|
|
|
; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_2f64_2f64_1111:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
2016-03-02 19:43:05 +08:00
|
|
|
; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
2016-01-10 03:59:27 +08:00
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <2 x double>, <2 x double>* %ptr
|
|
|
|
|
%ret = shufflevector <2 x double> %ld, <2 x double> undef, <2 x i32> <i32 1, i32 1>
|
|
|
|
|
ret <2 x double> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x double> @load_splat_4f64_2f64_1111(<2 x double>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_4f64_2f64_1111:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastsd 8(%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_4f64_2f64_1111:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastsd 8(%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <2 x double>, <2 x double>* %ptr
|
|
|
|
|
%ret = shufflevector <2 x double> %ld, <2 x double> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
|
|
|
ret <4 x double> %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x double> @load_splat_4f64_4f64_2222(<4 x double>* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: load_splat_4f64_4f64_2222:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastsd 16(%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: load_splat_4f64_4f64_2222:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastsd 16(%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 17:09:54 +08:00
|
|
|
entry:
|
|
|
|
|
%ld = load <4 x double>, <4 x double>* %ptr
|
|
|
|
|
%ret = shufflevector <4 x double> %ld, <4 x double> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
|
|
|
|
|
ret <4 x double> %ret
|
|
|
|
|
}
|
|
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
; Unsupported vbroadcasts
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: G:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2017-04-07 06:33:25 +08:00
|
|
|
; X32-NEXT: movl (%eax), %ecx
|
|
|
|
|
; X32-NEXT: movl 4(%eax), %eax
|
|
|
|
|
; X32-NEXT: vmovd %ecx, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: G:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
|
|
|
|
|
; X64-NEXT: retq
|
2011-08-17 10:29:19 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load i64, i64* %ptr, align 8
|
2011-08-17 10:29:19 +08:00
|
|
|
%vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1
|
|
|
|
|
ret <2 x i64> %vecinit2.i
|
|
|
|
|
}
|
2011-09-02 02:15:06 +08:00
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <2 x i64> @G2(i64* %ptr, i64* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: G2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: movl (%ecx), %edx
|
2017-04-07 06:33:25 +08:00
|
|
|
; X32-NEXT: movl 4(%ecx), %ecx
|
|
|
|
|
; X32-NEXT: movl %ecx, 4(%eax)
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: movl %edx, (%eax)
|
2017-04-07 06:33:25 +08:00
|
|
|
; X32-NEXT: vmovd %edx, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
|
|
|
|
|
; X32-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
|
2017-01-31 13:18:27 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: G2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: movq (%rdi), %rax
|
|
|
|
|
; X64-NEXT: movq %rax, (%rsi)
|
|
|
|
|
; X64-NEXT: vmovq %rax, %xmm0
|
|
|
|
|
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load i64, i64* %ptr, align 8
|
|
|
|
|
store i64 %q, i64* %ptr2, align 8 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1
|
|
|
|
|
ret <2 x i64> %vecinit2.i
|
|
|
|
|
}
|
|
|
|
|
|
2011-09-02 02:15:06 +08:00
|
|
|
define <4 x i32> @H(<4 x i32> %a) {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: H:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: H:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
|
|
|
|
|
; X64-NEXT: retq
|
2015-12-07 04:12:19 +08:00
|
|
|
entry:
|
2011-09-02 02:15:06 +08:00
|
|
|
%x = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
|
|
|
|
|
ret <4 x i32> %x
|
|
|
|
|
}
|
|
|
|
|
|
2012-01-10 16:23:59 +08:00
|
|
|
define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: I:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: I:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
|
|
|
|
; X64-NEXT: retq
|
2012-01-10 16:23:59 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load double, double* %ptr, align 4
|
2012-01-10 16:23:59 +08:00
|
|
|
%vecinit.i = insertelement <2 x double> undef, double %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
|
|
|
|
|
ret <2 x double> %vecinit2.i
|
|
|
|
|
}
|
2012-05-10 20:22:05 +08:00
|
|
|
|
2017-01-31 13:18:27 +08:00
|
|
|
define <2 x double> @I2(double* %ptr, double* %ptr2) nounwind uwtable readnone ssp {
|
|
|
|
|
; X32-LABEL: I2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; X32-NEXT: vmovsd %xmm0, (%eax)
|
|
|
|
|
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: I2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; X64-NEXT: vmovsd %xmm0, (%rsi)
|
|
|
|
|
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
|
|
|
|
%q = load double, double* %ptr, align 4
|
|
|
|
|
store double %q, double* %ptr2, align 4 ; to create a chain to prevent broadcast
|
|
|
|
|
%vecinit.i = insertelement <2 x double> undef, double %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
|
|
|
|
|
ret <2 x double> %vecinit2.i
|
|
|
|
|
}
|
|
|
|
|
|
2012-05-10 20:22:05 +08:00
|
|
|
define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: _RR:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X32-NEXT: vbroadcastss (%ecx), %xmm0
|
|
|
|
|
; X32-NEXT: movl (%eax), %eax
|
|
|
|
|
; X32-NEXT: movl %eax, (%eax)
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: _RR:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %xmm0
|
|
|
|
|
; X64-NEXT: movl (%rsi), %eax
|
|
|
|
|
; X64-NEXT: movl %eax, (%rax)
|
|
|
|
|
; X64-NEXT: retq
|
2012-05-10 20:22:05 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load float, float* %ptr, align 4
|
2012-05-10 20:22:05 +08:00
|
|
|
%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
|
|
|
|
|
%vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
|
|
|
|
|
%vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
|
|
|
|
|
%vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
|
|
|
|
|
; force a chain
|
2015-02-28 05:17:42 +08:00
|
|
|
%j = load i32, i32* %k, align 4
|
2012-05-10 20:22:05 +08:00
|
|
|
store i32 %j, i32* undef
|
|
|
|
|
ret <4 x float> %vecinit6.i
|
|
|
|
|
}
|
|
|
|
|
|
2012-05-10 20:39:13 +08:00
|
|
|
define <4 x float> @_RR2(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: _RR2:
|
|
|
|
|
; X32: ## BB#0: ## %entry
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %xmm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: _RR2:
|
|
|
|
|
; X64: ## BB#0: ## %entry
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %xmm0
|
|
|
|
|
; X64-NEXT: retq
|
2012-05-10 20:39:13 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%q = load float, float* %ptr, align 4
|
2012-05-10 20:39:13 +08:00
|
|
|
%v = insertelement <4 x float> undef, float %q, i32 0
|
|
|
|
|
%t = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
|
|
|
|
|
ret <4 x float> %t
|
|
|
|
|
}
|
|
|
|
|
|
Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.:
(concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4))
->
(BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4)
This fixes an issue with AVX, where a sequence was not recognized as a 256-bit
vbroadcast due to the concat_vectors.
llvm-svn: 201158
2014-02-11 23:42:46 +08:00
|
|
|
; These tests check that a vbroadcast instruction is used when we have a splat
|
|
|
|
|
; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
|
|
|
|
|
; (via the insertelements).
|
|
|
|
|
|
|
|
|
|
define <8 x float> @splat_concat1(float* %p) {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: splat_concat1:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: splat_concat1:
|
|
|
|
|
; X64: ## BB#0:
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load float, float* %p, align 4
|
Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.:
(concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4))
->
(BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4)
This fixes an issue with AVX, where a sequence was not recognized as a 256-bit
vbroadcast due to the concat_vectors.
llvm-svn: 201158
2014-02-11 23:42:46 +08:00
|
|
|
%2 = insertelement <4 x float> undef, float %1, i32 0
|
|
|
|
|
%3 = insertelement <4 x float> %2, float %1, i32 1
|
|
|
|
|
%4 = insertelement <4 x float> %3, float %1, i32 2
|
|
|
|
|
%5 = insertelement <4 x float> %4, float %1, i32 3
|
|
|
|
|
%6 = shufflevector <4 x float> %5, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
|
|
|
|
|
ret <8 x float> %6
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x float> @splat_concat2(float* %p) {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: splat_concat2:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastss (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: splat_concat2:
|
|
|
|
|
; X64: ## BB#0:
|
|
|
|
|
; X64-NEXT: vbroadcastss (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load float, float* %p, align 4
|
Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.:
(concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4))
->
(BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4)
This fixes an issue with AVX, where a sequence was not recognized as a 256-bit
vbroadcast due to the concat_vectors.
llvm-svn: 201158
2014-02-11 23:42:46 +08:00
|
|
|
%2 = insertelement <4 x float> undef, float %1, i32 0
|
|
|
|
|
%3 = insertelement <4 x float> %2, float %1, i32 1
|
|
|
|
|
%4 = insertelement <4 x float> %3, float %1, i32 2
|
|
|
|
|
%5 = insertelement <4 x float> %4, float %1, i32 3
|
|
|
|
|
%6 = insertelement <4 x float> undef, float %1, i32 0
|
|
|
|
|
%7 = insertelement <4 x float> %6, float %1, i32 1
|
|
|
|
|
%8 = insertelement <4 x float> %7, float %1, i32 2
|
|
|
|
|
%9 = insertelement <4 x float> %8, float %1, i32 3
|
|
|
|
|
%10 = shufflevector <4 x float> %5, <4 x float> %9, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
|
ret <8 x float> %10
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x double> @splat_concat3(double* %p) {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: splat_concat3:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastsd (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: splat_concat3:
|
|
|
|
|
; X64: ## BB#0:
|
|
|
|
|
; X64-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load double, double* %p, align 8
|
Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.:
(concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4))
->
(BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4)
This fixes an issue with AVX, where a sequence was not recognized as a 256-bit
vbroadcast due to the concat_vectors.
llvm-svn: 201158
2014-02-11 23:42:46 +08:00
|
|
|
%2 = insertelement <2 x double> undef, double %1, i32 0
|
|
|
|
|
%3 = insertelement <2 x double> %2, double %1, i32 1
|
|
|
|
|
%4 = shufflevector <2 x double> %3, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
|
|
|
|
|
ret <4 x double> %4
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x double> @splat_concat4(double* %p) {
|
2016-01-10 03:59:27 +08:00
|
|
|
; X32-LABEL: splat_concat4:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X32-NEXT: vbroadcastsd (%eax), %ymm0
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: splat_concat4:
|
|
|
|
|
; X64: ## BB#0:
|
|
|
|
|
; X64-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load double, double* %p, align 8
|
Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.:
(concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4))
->
(BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4)
This fixes an issue with AVX, where a sequence was not recognized as a 256-bit
vbroadcast due to the concat_vectors.
llvm-svn: 201158
2014-02-11 23:42:46 +08:00
|
|
|
%2 = insertelement <2 x double> undef, double %1, i32 0
|
|
|
|
|
%3 = insertelement <2 x double> %2, double %1, i32 1
|
|
|
|
|
%4 = insertelement <2 x double> undef, double %1, i32 0
|
|
|
|
|
%5 = insertelement <2 x double> %2, double %1, i32 1
|
|
|
|
|
%6 = shufflevector <2 x double> %3, <2 x double> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
|
ret <4 x double> %6
|
|
|
|
|
}
|
2016-09-29 01:59:30 +08:00
|
|
|
|
2017-08-07 20:24:33 +08:00
|
|
|
; PR34041
|
|
|
|
|
define <4 x double> @broadcast_shuffle_1000(double* %p) {
|
|
|
|
|
; X32-LABEL: broadcast_shuffle_1000:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2017-08-08 19:03:30 +08:00
|
|
|
; X32-NEXT: vbroadcastsd (%eax), %ymm0
|
2017-08-07 20:24:33 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: broadcast_shuffle_1000:
|
|
|
|
|
; X64: ## BB#0:
|
2017-08-08 19:03:30 +08:00
|
|
|
; X64-NEXT: vbroadcastsd (%rdi), %ymm0
|
2017-08-07 20:24:33 +08:00
|
|
|
; X64-NEXT: retq
|
|
|
|
|
%1 = load double, double* %p
|
|
|
|
|
%2 = insertelement <2 x double> undef, double %1, i32 0
|
|
|
|
|
%3 = shufflevector <2 x double> %2, <2 x double> undef, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
|
|
|
|
|
ret <4 x double> %3
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-08 06:20:06 +08:00
|
|
|
define <4 x double> @broadcast_shuffle1032(double* %p) {
|
|
|
|
|
; X32-LABEL: broadcast_shuffle1032:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
2017-08-08 19:03:30 +08:00
|
|
|
; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
|
|
|
|
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
2017-08-08 06:20:06 +08:00
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: broadcast_shuffle1032:
|
|
|
|
|
; X64: ## BB#0:
|
2017-08-08 19:03:30 +08:00
|
|
|
; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
|
|
|
|
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
2017-08-08 06:20:06 +08:00
|
|
|
; X64-NEXT: retq
|
|
|
|
|
%1 = load double, double* %p
|
|
|
|
|
%2 = insertelement <2 x double> undef, double %1, i32 1
|
|
|
|
|
%3 = insertelement <2 x double> undef, double %1, i32 0
|
|
|
|
|
%4 = shufflevector <2 x double> %2, <2 x double> %3, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
|
|
|
|
ret <4 x double> %4
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-29 01:59:30 +08:00
|
|
|
;
|
2016-10-02 23:59:15 +08:00
|
|
|
; When VBROADCAST replaces an existing load, ensure it still respects lifetime dependencies.
|
2016-09-29 01:59:30 +08:00
|
|
|
;
|
|
|
|
|
define float @broadcast_lifetime() nounwind {
|
|
|
|
|
; X32-LABEL: broadcast_lifetime:
|
|
|
|
|
; X32: ## BB#0:
|
|
|
|
|
; X32-NEXT: pushl %esi
|
2016-10-02 23:59:15 +08:00
|
|
|
; X32-NEXT: subl $56, %esp
|
2016-09-29 01:59:30 +08:00
|
|
|
; X32-NEXT: leal {{[0-9]+}}(%esp), %esi
|
|
|
|
|
; X32-NEXT: movl %esi, (%esp)
|
|
|
|
|
; X32-NEXT: calll _gfunc
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
2016-10-02 23:59:15 +08:00
|
|
|
; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp) ## 16-byte Spill
|
2016-09-29 01:59:30 +08:00
|
|
|
; X32-NEXT: movl %esi, (%esp)
|
|
|
|
|
; X32-NEXT: calll _gfunc
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; X32-NEXT: vpermilps $0, {{[0-9]+}}(%esp), %xmm1 ## 16-byte Folded Reload
|
|
|
|
|
; X32-NEXT: ## xmm1 = mem[0,0,0,0]
|
|
|
|
|
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
|
|
|
|
; X32-NEXT: vsubss %xmm1, %xmm0, %xmm0
|
2016-09-29 01:59:30 +08:00
|
|
|
; X32-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
|
|
|
|
|
; X32-NEXT: flds {{[0-9]+}}(%esp)
|
2016-10-02 23:59:15 +08:00
|
|
|
; X32-NEXT: addl $56, %esp
|
2016-09-29 01:59:30 +08:00
|
|
|
; X32-NEXT: popl %esi
|
|
|
|
|
; X32-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: broadcast_lifetime:
|
|
|
|
|
; X64: ## BB#0:
|
2016-10-02 23:59:15 +08:00
|
|
|
; X64-NEXT: subq $40, %rsp
|
2016-09-29 01:59:30 +08:00
|
|
|
; X64-NEXT: movq %rsp, %rdi
|
|
|
|
|
; X64-NEXT: callq _gfunc
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
2016-10-02 23:59:15 +08:00
|
|
|
; X64-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ## 16-byte Spill
|
2016-09-29 01:59:30 +08:00
|
|
|
; X64-NEXT: movq %rsp, %rdi
|
|
|
|
|
; X64-NEXT: callq _gfunc
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; X64-NEXT: vpermilps $0, {{[0-9]+}}(%rsp), %xmm1 ## 16-byte Folded Reload
|
|
|
|
|
; X64-NEXT: ## xmm1 = mem[0,0,0,0]
|
|
|
|
|
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
|
|
|
|
; X64-NEXT: vsubss %xmm1, %xmm0, %xmm0
|
2016-10-02 23:59:15 +08:00
|
|
|
; X64-NEXT: addq $40, %rsp
|
2016-09-29 01:59:30 +08:00
|
|
|
; X64-NEXT: retq
|
|
|
|
|
%1 = alloca <4 x float>, align 16
|
|
|
|
|
%2 = alloca <4 x float>, align 16
|
|
|
|
|
%3 = bitcast <4 x float>* %1 to i8*
|
|
|
|
|
%4 = bitcast <4 x float>* %2 to i8*
|
|
|
|
|
|
2017-04-11 04:18:21 +08:00
|
|
|
call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
|
2016-09-29 01:59:30 +08:00
|
|
|
call void @gfunc(<4 x float>* %1)
|
|
|
|
|
%5 = load <4 x float>, <4 x float>* %1, align 16
|
2017-04-11 04:18:21 +08:00
|
|
|
call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
|
2016-09-29 01:59:30 +08:00
|
|
|
|
2017-04-11 04:18:21 +08:00
|
|
|
call void @llvm.lifetime.start.p0i8(i64 16, i8* %4)
|
2016-09-29 01:59:30 +08:00
|
|
|
call void @gfunc(<4 x float>* %2)
|
|
|
|
|
%6 = load <4 x float>, <4 x float>* %2, align 16
|
2017-04-11 04:18:21 +08:00
|
|
|
call void @llvm.lifetime.end.p0i8(i64 16, i8* %4)
|
2016-09-29 01:59:30 +08:00
|
|
|
|
|
|
|
|
%7 = extractelement <4 x float> %5, i32 1
|
|
|
|
|
%8 = extractelement <4 x float> %6, i32 1
|
|
|
|
|
%9 = fsub float %8, %7
|
|
|
|
|
ret float %9
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
declare void @gfunc(<4 x float>*)
|
2017-04-11 04:18:21 +08:00
|
|
|
declare void @llvm.lifetime.start.p0i8(i64, i8*)
|
|
|
|
|
declare void @llvm.lifetime.end.p0i8(i64, i8*)
|