forked from OSchip/llvm-project
52 lines
1.6 KiB
LLVM
52 lines
1.6 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that the pipeliner cause an assert and correctly pipelines the
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; loop.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: [[REG0:r([0-9]+)]] = sath([[REG1:r([0-9]+)]])
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; CHECK: memh(r{{[0-9]+}}++#2) = [[REG0]].new
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; CHECK: [[REG1]] =
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; CHECK: endloop0
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define void @f0(i16* nocapture %a0, float* nocapture readonly %a1, float %a2, i32 %a3) {
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b0:
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%v0 = icmp sgt i32 %a3, 0
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br i1 %v0, label %b1, label %b2
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b1: ; preds = %b1, %b0
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%v1 = phi i32 [ %v11, %b1 ], [ 0, %b0 ]
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%v2 = phi i16* [ %v10, %b1 ], [ %a0, %b0 ]
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%v3 = phi float* [ %v4, %b1 ], [ %a1, %b0 ]
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%v4 = getelementptr inbounds float, float* %v3, i32 1
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%v5 = load float, float* %v3, align 4, !tbaa !0
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%v6 = fmul float %v5, %a2
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%v7 = tail call i32 @llvm.hexagon.F2.conv.sf2w(float %v6)
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%v8 = tail call i32 @llvm.hexagon.A2.sath(i32 %v7)
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%v9 = trunc i32 %v8 to i16
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%v10 = getelementptr inbounds i16, i16* %v2, i32 1
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store i16 %v9, i16* %v2, align 2, !tbaa !4
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%v11 = add nuw nsw i32 %v1, 1
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%v12 = icmp eq i32 %v11, %a3
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br i1 %v12, label %b2, label %b1
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b2: ; preds = %b1, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.sath(i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.F2.conv.sf2w(float) #0
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attributes #0 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"float", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"short", !2, i64 0}
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