forked from OSchip/llvm-project
26 lines
583 B
LLVM
26 lines
583 B
LLVM
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; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; CHECK: dcfetch(
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target triple = "hexagon"
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = alloca i32, align 4
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store i32 0, i32* %v0, align 4, !tbaa !0
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%v1 = bitcast i32* %v0 to i8*
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call void @llvm.hexagon.prefetch(i8* %v1)
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ret i32 0
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}
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; Function Attrs: nounwind
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declare void @llvm.hexagon.prefetch(i8*) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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