forked from OSchip/llvm-project
24 lines
692 B
LLVM
24 lines
692 B
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we generate new value stores.
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; CHECK: r[[REG:[0-9]+]] = sfadd(r{{[0-9]+}},r{{[0-9]+}})
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; CHECK-NOT: }
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; CHECK: memw({{.*}}) = r[[REG]].new
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define void @f0(float %a0, float %a1) #0 {
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b0:
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%v0 = alloca float, align 4
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%v1 = alloca float, align 4
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%v2 = alloca float*, align 4
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%v3 = alloca i32, align 4
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%v4 = load float, float* %v0, align 4
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%v5 = load float, float* %v1, align 4
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%v6 = fadd float %v5, %v4
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%v7 = load i32, i32* %v3, align 4
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%v8 = load float*, float** %v2, align 4
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%v9 = getelementptr inbounds float, float* %v8, i32 %v7
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store float %v6, float* %v9, align 4
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ret void
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}
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attributes #0 = { nounwind }
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