forked from OSchip/llvm-project
39 lines
1.8 KiB
LLVM
39 lines
1.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512F
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;
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; Combine tests involving SSE41 target shuffles (BLEND,INSERTPS,MOVZX)
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declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
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; FIXME: We can avoid the zero vector generation if we use PMOVZX instead
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define <16 x i8> @combine_vpshufb_as_movzx(<16 x i8> %a0) {
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; SSE-LABEL: combine_vpshufb_as_movzx:
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; SSE: # BB#0:
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vpshufb_as_movzx:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vpshufb_as_movzx:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: combine_vpshufb_as_movzx:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX512F-NEXT: retq
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%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -1, i8 -1, i8 -1, i8 -1, i8 undef, i8 undef, i8 undef, i8 undef, i8 -1, i8 -1, i8 -1, i8 -1>)
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ret <16 x i8> %res0
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}
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