2011-09-28 08:01:56 +08:00
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//===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
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2010-03-26 01:25:00 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2011-09-28 08:01:56 +08:00
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// This file contains the execution dependency fix pass.
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2010-03-26 01:25:00 +08:00
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//
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2011-09-28 08:01:56 +08:00
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// Some X86 SSE instructions like mov, and, or, xor are available in different
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2010-03-26 01:25:00 +08:00
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// variants for different operand types. These variant instructions are
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// equivalent, but on Nehalem and newer cpus there is extra latency
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2011-09-28 08:01:56 +08:00
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// transferring data between integer and floating point domains. ARM cores
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// have similar issues when they are configured with both VFP and NEON
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// pipelines.
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2010-03-26 01:25:00 +08:00
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//
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// This pass changes the variant instructions to minimize domain crossings.
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//
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//===----------------------------------------------------------------------===//
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2011-09-28 07:50:46 +08:00
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#include "llvm/CodeGen/Passes.h"
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2011-11-08 05:59:29 +08:00
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#include "llvm/ADT/PostOrderIterator.h"
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2014-12-18 03:13:47 +08:00
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#include "llvm/ADT/iterator_range.h"
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2013-12-14 14:52:56 +08:00
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#include "llvm/CodeGen/LivePhysRegs.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2016-08-18 03:07:40 +08:00
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#include "llvm/CodeGen/RegisterClassInfo.h"
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2010-04-05 02:00:21 +08:00
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#include "llvm/Support/Allocator.h"
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2010-03-26 01:25:00 +08:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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2014-08-05 05:25:23 +08:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2010-03-26 01:25:00 +08:00
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using namespace llvm;
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2014-04-22 10:02:50 +08:00
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#define DEBUG_TYPE "execution-fix"
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2010-04-01 04:32:51 +08:00
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/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
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2010-03-30 07:24:21 +08:00
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/// of execution domains.
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///
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/// An open DomainValue represents a set of instructions that can still switch
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/// execution domain. Multiple registers may refer to the same open
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/// DomainValue - they will eventually be collapsed to the same execution
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/// domain.
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///
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/// A collapsed DomainValue represents a single register that has been forced
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/// into one of more execution domains. There is a separate collapsed
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/// DomainValue for each register, but it may contain multiple execution
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/// domains. A register value is initially created in a single execution
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/// domain, but if we were forced to pay the penalty of a domain crossing, we
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2011-11-15 09:15:25 +08:00
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/// keep track of the fact that the register is now available in multiple
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2010-03-30 07:24:21 +08:00
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/// domains.
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2010-04-05 02:00:21 +08:00
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namespace {
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2010-03-30 07:24:21 +08:00
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struct DomainValue {
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// Basic reference counting.
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unsigned Refs;
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2010-04-05 05:27:26 +08:00
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// Bitmask of available domains. For an open DomainValue, it is the still
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// possible domains for collapsing. For a collapsed DomainValue it is the
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// domains where the register is available for free.
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unsigned AvailableDomains;
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2010-03-30 07:24:21 +08:00
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2011-11-09 08:06:18 +08:00
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// Pointer to the next DomainValue in a chain. When two DomainValues are
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// merged, Victim.Next is set to point to Victor, so old DomainValue
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2012-06-02 18:20:22 +08:00
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// references can be updated by following the chain.
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2011-11-09 08:06:18 +08:00
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DomainValue *Next;
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2010-03-30 07:24:21 +08:00
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// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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2010-04-05 05:27:26 +08:00
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// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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2010-03-30 07:24:21 +08:00
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// track of the domains where the registers are already available.
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2010-04-05 05:27:26 +08:00
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bool isCollapsed() const { return Instrs.empty(); }
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2010-03-30 07:24:21 +08:00
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2010-04-05 05:27:26 +08:00
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// Is domain available?
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bool hasDomain(unsigned domain) const {
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2014-12-16 22:04:11 +08:00
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assert(domain <
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static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
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2014-12-16 02:48:43 +08:00
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"undefined behavior");
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2010-04-05 05:27:26 +08:00
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return AvailableDomains & (1u << domain);
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2010-03-30 07:24:21 +08:00
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}
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2010-03-31 04:04:01 +08:00
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// Mark domain as available.
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2010-04-05 05:27:26 +08:00
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void addDomain(unsigned domain) {
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AvailableDomains |= 1u << domain;
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2010-03-30 07:24:21 +08:00
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}
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2010-04-05 05:27:26 +08:00
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// Restrict to a single domain available.
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void setSingleDomain(unsigned domain) {
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AvailableDomains = 1u << domain;
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}
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// Return bitmask of domains that are available and in mask.
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unsigned getCommonDomains(unsigned mask) const {
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return AvailableDomains & mask;
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}
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// First domain available.
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unsigned getFirstDomain() const {
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2013-05-25 06:23:49 +08:00
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return countTrailingZeros(AvailableDomains);
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2010-03-31 04:04:01 +08:00
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}
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2011-11-09 07:26:00 +08:00
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DomainValue() : Refs(0) { clear(); }
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2010-03-30 07:24:21 +08:00
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2011-11-09 08:06:18 +08:00
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// Clear this DomainValue and point to next which has all its data.
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2010-03-30 07:24:21 +08:00
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void clear() {
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2011-11-15 09:15:25 +08:00
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AvailableDomains = 0;
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2014-04-14 08:51:57 +08:00
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Next = nullptr;
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2010-03-30 07:24:21 +08:00
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Instrs.clear();
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}
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};
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2015-06-23 17:49:53 +08:00
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}
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2010-03-30 07:24:21 +08:00
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2011-11-15 09:15:25 +08:00
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namespace {
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2015-03-16 02:16:04 +08:00
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/// Information about a live register.
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2011-11-15 09:15:25 +08:00
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struct LiveReg {
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/// Value currently in this register, or NULL when no value is being tracked.
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/// This counts as a DomainValue reference.
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DomainValue *Value;
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/// Instruction that defined this register, relative to the beginning of the
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/// current basic block. When a LiveReg is used to represent a live-out
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/// register, this value is relative to the end of the basic block, so it
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/// will be a negative number.
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int Def;
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};
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2015-03-16 02:11:35 +08:00
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} // anonymous namespace
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2011-11-15 09:15:25 +08:00
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2010-04-05 02:00:21 +08:00
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namespace {
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2011-09-28 08:01:56 +08:00
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class ExeDepsFix : public MachineFunctionPass {
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2010-03-26 01:25:00 +08:00
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static char ID;
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2010-04-05 02:00:21 +08:00
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SpecificBumpPtrAllocator<DomainValue> Allocator;
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SmallVector<DomainValue*,16> Avail;
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2010-03-26 01:25:00 +08:00
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2011-09-28 07:50:46 +08:00
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const TargetRegisterClass *const RC;
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2010-03-26 01:25:00 +08:00
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MachineFunction *MF;
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2011-09-28 07:50:46 +08:00
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const TargetInstrInfo *TII;
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2010-03-30 07:24:21 +08:00
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const TargetRegisterInfo *TRI;
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2016-08-18 03:07:40 +08:00
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RegisterClassInfo RegClassInfo;
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2014-12-18 03:13:47 +08:00
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std::vector<SmallVector<int, 1>> AliasMap;
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2011-09-28 07:50:46 +08:00
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const unsigned NumRegs;
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2011-11-15 09:15:25 +08:00
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LiveReg *LiveRegs;
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typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
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2010-03-31 04:04:01 +08:00
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LiveOutMap LiveOuts;
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2011-11-15 09:15:25 +08:00
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2013-10-15 06:19:03 +08:00
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/// List of undefined register reads in this block in forward order.
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std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
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/// Storage for register unit liveness.
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2013-12-14 14:52:56 +08:00
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LivePhysRegs LiveRegSet;
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2013-10-15 06:19:03 +08:00
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2011-11-15 09:15:25 +08:00
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/// Current instruction number.
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/// The first instruction in each basic block is 0.
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int CurInstr;
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/// True when the current block has a predecessor that hasn't been visited
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/// yet.
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bool SeenUnknownBackEdge;
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2010-03-30 07:24:21 +08:00
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2010-03-26 01:25:00 +08:00
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public:
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2011-09-28 08:01:56 +08:00
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ExeDepsFix(const TargetRegisterClass *rc)
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2011-09-28 07:50:46 +08:00
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: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
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2010-03-26 01:25:00 +08:00
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2014-03-07 17:26:03 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2010-03-26 01:25:00 +08:00
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2014-03-07 17:26:03 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2010-03-26 01:25:00 +08:00
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2016-04-05 01:09:25 +08:00
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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2016-08-25 09:27:13 +08:00
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MachineFunctionProperties::Property::NoVRegs);
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2016-04-05 01:09:25 +08:00
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}
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2016-10-01 10:56:57 +08:00
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StringRef getPassName() const override { return "Execution dependency fix"; }
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2010-03-26 01:25:00 +08:00
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private:
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2014-12-18 03:13:47 +08:00
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iterator_range<SmallVectorImpl<int>::const_iterator>
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2015-03-07 02:56:20 +08:00
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regIndices(unsigned Reg) const;
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2010-03-30 07:24:21 +08:00
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2010-04-05 02:00:21 +08:00
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// DomainValue allocation.
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2011-11-09 05:57:47 +08:00
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DomainValue *alloc(int domain = -1);
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2011-11-09 08:06:18 +08:00
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DomainValue *retain(DomainValue *DV) {
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if (DV) ++DV->Refs;
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return DV;
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}
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2011-11-09 05:57:44 +08:00
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void release(DomainValue*);
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2011-11-09 08:06:18 +08:00
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DomainValue *resolve(DomainValue*&);
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2010-04-05 02:00:21 +08:00
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2010-03-30 07:24:21 +08:00
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// LiveRegs manipulations.
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2011-11-09 05:57:47 +08:00
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void setLiveReg(int rx, DomainValue *DV);
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void kill(int rx);
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void force(int rx, unsigned domain);
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void collapse(DomainValue *dv, unsigned domain);
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bool merge(DomainValue *A, DomainValue *B);
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2010-03-30 07:24:21 +08:00
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2011-11-15 09:15:25 +08:00
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void enterBasicBlock(MachineBasicBlock*);
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2011-11-08 05:40:27 +08:00
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void leaveBasicBlock(MachineBasicBlock*);
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void visitInstr(MachineInstr*);
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2011-11-15 09:15:25 +08:00
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void processDefs(MachineInstr*, bool Kill);
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2010-03-30 07:24:21 +08:00
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitHardInstr(MachineInstr*, unsigned domain);
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2016-08-11 15:32:08 +08:00
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void pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref);
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2013-10-15 06:19:03 +08:00
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bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
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void processUndefReads(MachineBasicBlock*);
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2010-03-26 01:25:00 +08:00
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};
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2015-06-23 17:49:53 +08:00
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}
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2010-03-26 01:25:00 +08:00
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2011-09-28 08:01:56 +08:00
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char ExeDepsFix::ID = 0;
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2010-03-26 01:25:00 +08:00
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2015-03-07 02:56:20 +08:00
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/// Translate TRI register number to a list of indices into our smaller tables
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2014-12-18 03:13:47 +08:00
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/// of interesting registers.
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iterator_range<SmallVectorImpl<int>::const_iterator>
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2015-03-07 02:56:20 +08:00
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ExeDepsFix::regIndices(unsigned Reg) const {
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2011-09-28 07:50:46 +08:00
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assert(Reg < AliasMap.size() && "Invalid register");
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2014-12-18 03:13:47 +08:00
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const auto &Entry = AliasMap[Reg];
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return make_range(Entry.begin(), Entry.end());
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2010-03-30 07:24:21 +08:00
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}
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2011-11-09 05:57:47 +08:00
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DomainValue *ExeDepsFix::alloc(int domain) {
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2010-04-05 02:00:21 +08:00
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DomainValue *dv = Avail.empty() ?
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new(Allocator.Allocate()) DomainValue :
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Avail.pop_back_val();
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if (domain >= 0)
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2010-04-05 05:27:26 +08:00
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dv->addDomain(domain);
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2011-11-09 07:26:00 +08:00
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assert(dv->Refs == 0 && "Reference count wasn't cleared");
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2011-11-09 08:06:18 +08:00
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assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
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2010-04-05 02:00:21 +08:00
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return dv;
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}
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2015-03-16 02:16:04 +08:00
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/// Release a reference to DV. When the last reference is released,
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2011-11-09 05:57:44 +08:00
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/// collapse if needed.
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void ExeDepsFix::release(DomainValue *DV) {
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2011-11-09 08:06:18 +08:00
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while (DV) {
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assert(DV->Refs && "Bad DomainValue");
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if (--DV->Refs)
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return;
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// There are no more DV references. Collapse any contained instructions.
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if (DV->AvailableDomains && !DV->isCollapsed())
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collapse(DV, DV->getFirstDomain());
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DomainValue *Next = DV->Next;
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DV->clear();
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Avail.push_back(DV);
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// Also release the next DomainValue in the chain.
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DV = Next;
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}
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}
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2011-11-09 05:57:44 +08:00
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2015-03-16 02:16:04 +08:00
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/// Follow the chain of dead DomainValues until a live DomainValue is reached.
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/// Update the referenced pointer when necessary.
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2011-11-09 08:06:18 +08:00
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DomainValue *ExeDepsFix::resolve(DomainValue *&DVRef) {
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DomainValue *DV = DVRef;
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if (!DV || !DV->Next)
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return DV;
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// DV has a chain. Find the end.
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do DV = DV->Next;
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while (DV->Next);
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// Update DVRef to point to DV.
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retain(DV);
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release(DVRef);
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DVRef = DV;
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return DV;
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2010-04-05 02:00:21 +08:00
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}
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2010-03-30 07:24:21 +08:00
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/// Set LiveRegs[rx] = dv, updating reference counts.
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2011-11-09 05:57:47 +08:00
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void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) {
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2010-03-31 04:04:01 +08:00
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assert(unsigned(rx) < NumRegs && "Invalid index");
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2011-11-15 09:15:25 +08:00
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assert(LiveRegs && "Must enter basic block first.");
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2010-03-31 04:04:01 +08:00
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2011-11-15 09:15:25 +08:00
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|
if (LiveRegs[rx].Value == dv)
|
2010-03-30 07:24:21 +08:00
|
|
|
return;
|
2011-11-15 09:15:25 +08:00
|
|
|
if (LiveRegs[rx].Value)
|
|
|
|
release(LiveRegs[rx].Value);
|
|
|
|
LiveRegs[rx].Value = retain(dv);
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Kill register rx, recycle or collapse any DomainValue.
|
2011-11-09 05:57:47 +08:00
|
|
|
void ExeDepsFix::kill(int rx) {
|
2010-03-31 04:04:01 +08:00
|
|
|
assert(unsigned(rx) < NumRegs && "Invalid index");
|
2011-11-15 09:15:25 +08:00
|
|
|
assert(LiveRegs && "Must enter basic block first.");
|
|
|
|
if (!LiveRegs[rx].Value)
|
|
|
|
return;
|
2010-03-30 07:24:21 +08:00
|
|
|
|
2011-11-15 09:15:25 +08:00
|
|
|
release(LiveRegs[rx].Value);
|
2014-04-14 08:51:57 +08:00
|
|
|
LiveRegs[rx].Value = nullptr;
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Force register rx into domain.
|
2011-11-09 05:57:47 +08:00
|
|
|
void ExeDepsFix::force(int rx, unsigned domain) {
|
2010-03-31 04:04:01 +08:00
|
|
|
assert(unsigned(rx) < NumRegs && "Invalid index");
|
2011-11-15 09:15:25 +08:00
|
|
|
assert(LiveRegs && "Must enter basic block first.");
|
|
|
|
if (DomainValue *dv = LiveRegs[rx].Value) {
|
2010-04-05 05:27:26 +08:00
|
|
|
if (dv->isCollapsed())
|
|
|
|
dv->addDomain(domain);
|
2010-04-07 03:48:56 +08:00
|
|
|
else if (dv->hasDomain(domain))
|
2011-11-09 05:57:47 +08:00
|
|
|
collapse(dv, domain);
|
2010-04-07 03:48:56 +08:00
|
|
|
else {
|
2011-09-28 08:01:56 +08:00
|
|
|
// This is an incompatible open DomainValue. Collapse it to whatever and
|
|
|
|
// force the new value into domain. This costs a domain crossing.
|
2011-11-09 05:57:47 +08:00
|
|
|
collapse(dv, dv->getFirstDomain());
|
2011-11-15 09:15:25 +08:00
|
|
|
assert(LiveRegs[rx].Value && "Not live after collapse?");
|
|
|
|
LiveRegs[rx].Value->addDomain(domain);
|
2010-04-07 03:48:56 +08:00
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
} else {
|
2010-03-31 04:04:01 +08:00
|
|
|
// Set up basic collapsed DomainValue.
|
2011-11-09 05:57:47 +08:00
|
|
|
setLiveReg(rx, alloc(domain));
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Collapse open DomainValue into given domain. If there are multiple
|
|
|
|
/// registers using dv, they each get a unique collapsed DomainValue.
|
2011-11-09 05:57:47 +08:00
|
|
|
void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) {
|
2010-04-05 05:27:26 +08:00
|
|
|
assert(dv->hasDomain(domain) && "Cannot collapse");
|
2010-03-30 07:24:21 +08:00
|
|
|
|
|
|
|
// Collapse all the instructions.
|
2010-04-05 05:27:26 +08:00
|
|
|
while (!dv->Instrs.empty())
|
2016-06-30 08:01:54 +08:00
|
|
|
TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain);
|
2010-04-05 05:27:26 +08:00
|
|
|
dv->setSingleDomain(domain);
|
2010-03-30 07:24:21 +08:00
|
|
|
|
|
|
|
// If there are multiple users, give them new, unique DomainValues.
|
2010-04-05 02:00:21 +08:00
|
|
|
if (LiveRegs && dv->Refs > 1)
|
2010-03-31 04:04:01 +08:00
|
|
|
for (unsigned rx = 0; rx != NumRegs; ++rx)
|
2011-11-15 09:15:25 +08:00
|
|
|
if (LiveRegs[rx].Value == dv)
|
2011-11-09 05:57:47 +08:00
|
|
|
setLiveReg(rx, alloc(domain));
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
2015-03-16 02:16:04 +08:00
|
|
|
/// All instructions and registers in B are moved to A, and B is released.
|
2011-11-09 05:57:47 +08:00
|
|
|
bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) {
|
2010-04-05 05:27:26 +08:00
|
|
|
assert(!A->isCollapsed() && "Cannot merge into collapsed");
|
|
|
|
assert(!B->isCollapsed() && "Cannot merge from collapsed");
|
2010-04-01 04:05:12 +08:00
|
|
|
if (A == B)
|
2010-04-01 01:13:16 +08:00
|
|
|
return true;
|
2010-04-05 05:27:26 +08:00
|
|
|
// Restrict to the domains that A and B have in common.
|
|
|
|
unsigned common = A->getCommonDomains(B->AvailableDomains);
|
|
|
|
if (!common)
|
2010-03-30 07:24:21 +08:00
|
|
|
return false;
|
2010-04-05 05:27:26 +08:00
|
|
|
A->AvailableDomains = common;
|
2010-03-30 07:24:21 +08:00
|
|
|
A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
|
2011-11-09 04:57:04 +08:00
|
|
|
|
|
|
|
// Clear the old DomainValue so we won't try to swizzle instructions twice.
|
2011-11-09 07:26:00 +08:00
|
|
|
B->clear();
|
2011-11-09 08:06:18 +08:00
|
|
|
// All uses of B are referred to A.
|
|
|
|
B->Next = retain(A);
|
2011-11-09 04:57:04 +08:00
|
|
|
|
2014-12-16 02:48:43 +08:00
|
|
|
for (unsigned rx = 0; rx != NumRegs; ++rx) {
|
|
|
|
assert(LiveRegs && "no space allocated for live registers");
|
2011-11-15 09:15:25 +08:00
|
|
|
if (LiveRegs[rx].Value == B)
|
2011-11-09 05:57:47 +08:00
|
|
|
setLiveReg(rx, A);
|
2014-12-16 02:48:43 +08:00
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2015-03-16 02:16:04 +08:00
|
|
|
/// Set up LiveRegs by merging predecessor live-out values.
|
2011-11-15 09:15:25 +08:00
|
|
|
void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
|
2011-11-09 09:06:56 +08:00
|
|
|
// Detect back-edges from predecessors we haven't processed yet.
|
2011-11-15 09:15:25 +08:00
|
|
|
SeenUnknownBackEdge = false;
|
2011-11-09 09:06:56 +08:00
|
|
|
|
2011-11-15 09:15:25 +08:00
|
|
|
// Reset instruction counter in each basic block.
|
|
|
|
CurInstr = 0;
|
|
|
|
|
2013-10-15 06:19:03 +08:00
|
|
|
// Set up UndefReads to track undefined register reads.
|
|
|
|
UndefReads.clear();
|
2013-12-14 14:52:56 +08:00
|
|
|
LiveRegSet.clear();
|
2013-10-15 06:19:03 +08:00
|
|
|
|
2011-11-15 09:15:25 +08:00
|
|
|
// Set up LiveRegs to represent registers entering MBB.
|
|
|
|
if (!LiveRegs)
|
|
|
|
LiveRegs = new LiveReg[NumRegs];
|
|
|
|
|
|
|
|
// Default values are 'nothing happened a long time ago'.
|
|
|
|
for (unsigned rx = 0; rx != NumRegs; ++rx) {
|
2014-04-14 08:51:57 +08:00
|
|
|
LiveRegs[rx].Value = nullptr;
|
2011-11-15 09:15:25 +08:00
|
|
|
LiveRegs[rx].Def = -(1 << 20);
|
|
|
|
}
|
|
|
|
|
|
|
|
// This is the entry block.
|
|
|
|
if (MBB->pred_empty()) {
|
2015-09-10 02:08:03 +08:00
|
|
|
for (const auto &LI : MBB->liveins()) {
|
|
|
|
for (int rx : regIndices(LI.PhysReg)) {
|
2014-12-18 03:13:47 +08:00
|
|
|
// Treat function live-ins as if they were defined just before the first
|
|
|
|
// instruction. Usually, function arguments are set up immediately
|
|
|
|
// before the call.
|
|
|
|
LiveRegs[rx].Def = -1;
|
|
|
|
}
|
2011-11-15 09:15:25 +08:00
|
|
|
}
|
|
|
|
DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try to coalesce live-out registers from predecessors.
|
|
|
|
for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
|
|
|
|
pe = MBB->pred_end(); pi != pe; ++pi) {
|
|
|
|
LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
|
|
|
|
if (fi == LiveOuts.end()) {
|
|
|
|
SeenUnknownBackEdge = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
assert(fi->second && "Can't have NULL entries");
|
|
|
|
|
|
|
|
for (unsigned rx = 0; rx != NumRegs; ++rx) {
|
|
|
|
// Use the most recent predecessor def for each register.
|
|
|
|
LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
|
|
|
|
|
|
|
|
DomainValue *pdv = resolve(fi->second[rx].Value);
|
|
|
|
if (!pdv)
|
2011-11-09 09:06:56 +08:00
|
|
|
continue;
|
2011-11-15 09:15:25 +08:00
|
|
|
if (!LiveRegs[rx].Value) {
|
2011-11-09 05:57:47 +08:00
|
|
|
setLiveReg(rx, pdv);
|
2010-04-01 04:32:51 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// We have a live DomainValue from more than one predecessor.
|
2011-11-15 09:15:25 +08:00
|
|
|
if (LiveRegs[rx].Value->isCollapsed()) {
|
2014-05-21 01:11:11 +08:00
|
|
|
// We are already collapsed, but predecessor is not. Force it.
|
2011-11-15 09:15:25 +08:00
|
|
|
unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
|
|
|
|
if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
|
|
|
|
collapse(pdv, Domain);
|
2010-04-01 04:32:51 +08:00
|
|
|
continue;
|
2010-03-31 04:04:01 +08:00
|
|
|
}
|
2010-04-05 02:00:21 +08:00
|
|
|
|
2010-04-01 04:32:51 +08:00
|
|
|
// Currently open, merge in predecessor.
|
2010-04-05 05:27:26 +08:00
|
|
|
if (!pdv->isCollapsed())
|
2011-11-15 09:15:25 +08:00
|
|
|
merge(LiveRegs[rx].Value, pdv);
|
2010-04-01 04:32:51 +08:00
|
|
|
else
|
2011-11-09 05:57:47 +08:00
|
|
|
force(rx, pdv->getFirstDomain());
|
2010-03-31 04:04:01 +08:00
|
|
|
}
|
|
|
|
}
|
2011-11-15 09:15:25 +08:00
|
|
|
DEBUG(dbgs() << "BB#" << MBB->getNumber()
|
|
|
|
<< (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
2011-11-08 05:40:27 +08:00
|
|
|
void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
|
2011-11-15 09:15:25 +08:00
|
|
|
assert(LiveRegs && "Must enter basic block first.");
|
2011-11-08 05:40:27 +08:00
|
|
|
// Save live registers at end of MBB - used by enterBasicBlock().
|
2011-11-09 09:06:56 +08:00
|
|
|
// Also use LiveOuts as a visited set to detect back-edges.
|
2011-11-15 09:15:25 +08:00
|
|
|
bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
|
|
|
|
|
|
|
|
if (First) {
|
|
|
|
// LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
|
|
|
|
// the end of this block instead of the beginning.
|
|
|
|
for (unsigned i = 0, e = NumRegs; i != e; ++i)
|
|
|
|
LiveRegs[i].Def -= CurInstr;
|
|
|
|
} else {
|
2011-11-09 09:06:56 +08:00
|
|
|
// Insertion failed, this must be the second pass.
|
|
|
|
// Release all the DomainValues instead of keeping them.
|
|
|
|
for (unsigned i = 0, e = NumRegs; i != e; ++i)
|
2011-11-15 09:15:25 +08:00
|
|
|
release(LiveRegs[i].Value);
|
2011-11-09 09:06:56 +08:00
|
|
|
delete[] LiveRegs;
|
|
|
|
}
|
2014-04-14 08:51:57 +08:00
|
|
|
LiveRegs = nullptr;
|
2011-11-08 05:40:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void ExeDepsFix::visitInstr(MachineInstr *MI) {
|
|
|
|
if (MI->isDebugValue())
|
|
|
|
return;
|
2011-11-15 09:15:25 +08:00
|
|
|
|
|
|
|
// Update instructions with explicit execution domains.
|
2016-06-30 08:01:54 +08:00
|
|
|
std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(*MI);
|
2011-11-15 09:15:25 +08:00
|
|
|
if (DomP.first) {
|
|
|
|
if (DomP.second)
|
|
|
|
visitSoftInstr(MI, DomP.second);
|
2011-11-08 05:40:27 +08:00
|
|
|
else
|
2011-11-15 09:15:25 +08:00
|
|
|
visitHardInstr(MI, DomP.first);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Process defs to track register ages, and kill values clobbered by generic
|
|
|
|
// instructions.
|
|
|
|
processDefs(MI, !DomP.first);
|
|
|
|
}
|
|
|
|
|
2016-08-11 15:32:08 +08:00
|
|
|
/// \brief Helps avoid false dependencies on undef registers by updating the
|
|
|
|
/// machine instructions' undef operand to use a register that the instruction
|
|
|
|
/// is truly dependent on, or use a register with clearance higher than Pref.
|
|
|
|
void ExeDepsFix::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
|
|
|
|
unsigned Pref) {
|
|
|
|
MachineOperand &MO = MI->getOperand(OpIdx);
|
|
|
|
assert(MO.isUndef() && "Expected undef machine operand");
|
|
|
|
|
|
|
|
unsigned OriginalReg = MO.getReg();
|
|
|
|
|
|
|
|
// Update only undef operands that are mapped to one register.
|
|
|
|
if (AliasMap[OriginalReg].size() != 1)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Get the undef operand's register class
|
|
|
|
const TargetRegisterClass *OpRC =
|
|
|
|
TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
|
|
|
|
|
|
|
|
// If the instruction has a true dependency, we can hide the false depdency
|
|
|
|
// behind it.
|
|
|
|
for (MachineOperand &CurrMO : MI->operands()) {
|
|
|
|
if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
|
|
|
|
!OpRC->contains(CurrMO.getReg()))
|
|
|
|
continue;
|
|
|
|
// We found a true dependency - replace the undef register with the true
|
|
|
|
// dependency.
|
|
|
|
MO.setReg(CurrMO.getReg());
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Go over all registers in the register class and find the register with
|
|
|
|
// max clearance or clearance higher than Pref.
|
|
|
|
unsigned MaxClearance = 0;
|
|
|
|
unsigned MaxClearanceReg = OriginalReg;
|
2016-08-18 03:07:40 +08:00
|
|
|
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
|
|
|
|
for (auto Reg : Order) {
|
2016-08-17 19:40:21 +08:00
|
|
|
assert(AliasMap[Reg].size() == 1 &&
|
|
|
|
"Reg is expected to be mapped to a single index");
|
|
|
|
int RCrx = *regIndices(Reg).begin();
|
|
|
|
unsigned Clearance = CurInstr - LiveRegs[RCrx].Def;
|
2016-08-11 15:32:08 +08:00
|
|
|
if (Clearance <= MaxClearance)
|
|
|
|
continue;
|
|
|
|
MaxClearance = Clearance;
|
2016-08-17 19:40:21 +08:00
|
|
|
MaxClearanceReg = Reg;
|
2016-08-11 15:32:08 +08:00
|
|
|
|
|
|
|
if (MaxClearance > Pref)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update the operand if we found a register with better clearance.
|
|
|
|
if (MaxClearanceReg != OriginalReg)
|
|
|
|
MO.setReg(MaxClearanceReg);
|
|
|
|
}
|
|
|
|
|
2013-10-15 06:19:03 +08:00
|
|
|
/// \brief Return true to if it makes sense to break dependence on a partial def
|
|
|
|
/// or undef use.
|
|
|
|
bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
|
|
|
|
unsigned Pref) {
|
2014-12-18 03:13:47 +08:00
|
|
|
unsigned reg = MI->getOperand(OpIdx).getReg();
|
2015-03-07 02:56:20 +08:00
|
|
|
for (int rx : regIndices(reg)) {
|
2014-12-18 03:13:47 +08:00
|
|
|
unsigned Clearance = CurInstr - LiveRegs[rx].Def;
|
|
|
|
DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
|
2013-10-15 06:19:03 +08:00
|
|
|
|
2014-12-18 03:13:47 +08:00
|
|
|
if (Pref > Clearance) {
|
|
|
|
DEBUG(dbgs() << ": Break dependency.\n");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// The current clearance seems OK, but we may be ignoring a def from a
|
|
|
|
// back-edge.
|
|
|
|
if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) {
|
|
|
|
DEBUG(dbgs() << ": OK .\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// A def from an unprocessed back-edge may make us break this dependency.
|
|
|
|
DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
|
2013-10-15 06:19:03 +08:00
|
|
|
return false;
|
|
|
|
}
|
2014-12-18 03:13:47 +08:00
|
|
|
return true;
|
2013-10-15 06:19:03 +08:00
|
|
|
}
|
|
|
|
|
2011-11-15 09:15:25 +08:00
|
|
|
// Update def-ages for registers defined by MI.
|
|
|
|
// If Kill is set, also kill off DomainValues clobbered by the defs.
|
2013-10-15 06:19:03 +08:00
|
|
|
//
|
|
|
|
// Also break dependencies on partial defs and undef uses.
|
2011-11-15 09:15:25 +08:00
|
|
|
void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
|
|
|
|
assert(!MI->isDebugValue() && "Won't process debug values");
|
2013-10-15 06:19:03 +08:00
|
|
|
|
|
|
|
// Break dependence on undef uses. Do this before updating LiveRegs below.
|
|
|
|
unsigned OpNum;
|
2016-06-30 08:01:54 +08:00
|
|
|
unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
|
2013-10-15 06:19:03 +08:00
|
|
|
if (Pref) {
|
2016-08-11 15:32:08 +08:00
|
|
|
pickBestRegisterForUndef(MI, OpNum, Pref);
|
2013-10-15 06:19:03 +08:00
|
|
|
if (shouldBreakDependence(MI, OpNum, Pref))
|
|
|
|
UndefReads.push_back(std::make_pair(MI, OpNum));
|
|
|
|
}
|
2011-11-15 09:15:25 +08:00
|
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
|
|
for (unsigned i = 0,
|
2011-12-07 15:15:52 +08:00
|
|
|
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
|
2011-11-15 09:15:25 +08:00
|
|
|
i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
if (MO.isUse())
|
|
|
|
continue;
|
2015-03-07 02:56:20 +08:00
|
|
|
for (int rx : regIndices(MO.getReg())) {
|
2014-12-18 03:13:47 +08:00
|
|
|
// This instruction explicitly defines rx.
|
|
|
|
DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
|
|
|
|
<< '\t' << *MI);
|
|
|
|
|
|
|
|
// Check clearance before partial register updates.
|
|
|
|
// Call breakDependence before setting LiveRegs[rx].Def.
|
2016-06-30 08:01:54 +08:00
|
|
|
unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
|
2014-12-18 03:13:47 +08:00
|
|
|
if (Pref && shouldBreakDependence(MI, i, Pref))
|
2016-06-30 08:01:54 +08:00
|
|
|
TII->breakPartialRegDependency(*MI, i, TRI);
|
2014-12-18 03:13:47 +08:00
|
|
|
|
|
|
|
// How many instructions since rx was last written?
|
|
|
|
LiveRegs[rx].Def = CurInstr;
|
|
|
|
|
|
|
|
// Kill off domains redefined by generic instructions.
|
|
|
|
if (Kill)
|
|
|
|
kill(rx);
|
|
|
|
}
|
2013-10-15 06:19:03 +08:00
|
|
|
}
|
|
|
|
++CurInstr;
|
|
|
|
}
|
2011-11-15 09:15:30 +08:00
|
|
|
|
2013-10-15 06:19:03 +08:00
|
|
|
/// \break Break false dependencies on undefined register reads.
|
|
|
|
///
|
|
|
|
/// Walk the block backward computing precise liveness. This is expensive, so we
|
|
|
|
/// only do it on demand. Note that the occurrence of undefined register reads
|
|
|
|
/// that should be broken is very rare, but when they occur we may have many in
|
|
|
|
/// a single block.
|
|
|
|
void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
|
|
|
|
if (UndefReads.empty())
|
|
|
|
return;
|
2011-11-15 09:15:30 +08:00
|
|
|
|
2013-10-15 06:19:03 +08:00
|
|
|
// Collect this block's live out register units.
|
2013-12-14 14:52:56 +08:00
|
|
|
LiveRegSet.init(TRI);
|
2016-05-03 08:08:46 +08:00
|
|
|
// We do not need to care about pristine registers as they are just preserved
|
|
|
|
// but not actually used in the function.
|
2016-05-03 08:24:32 +08:00
|
|
|
LiveRegSet.addLiveOutsNoPristines(*MBB);
|
2013-12-14 14:52:56 +08:00
|
|
|
|
2013-10-15 06:19:03 +08:00
|
|
|
MachineInstr *UndefMI = UndefReads.back().first;
|
|
|
|
unsigned OpIdx = UndefReads.back().second;
|
2011-11-15 09:15:25 +08:00
|
|
|
|
2015-07-25 05:13:43 +08:00
|
|
|
for (MachineInstr &I : make_range(MBB->rbegin(), MBB->rend())) {
|
2013-12-14 06:23:54 +08:00
|
|
|
// Update liveness, including the current instruction's defs.
|
2015-07-25 05:13:43 +08:00
|
|
|
LiveRegSet.stepBackward(I);
|
2013-10-15 11:39:43 +08:00
|
|
|
|
2015-07-25 05:13:43 +08:00
|
|
|
if (UndefMI == &I) {
|
2013-12-14 14:52:56 +08:00
|
|
|
if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
|
2016-06-30 08:01:54 +08:00
|
|
|
TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI);
|
2013-10-15 06:19:03 +08:00
|
|
|
|
|
|
|
UndefReads.pop_back();
|
|
|
|
if (UndefReads.empty())
|
|
|
|
return;
|
|
|
|
|
|
|
|
UndefMI = UndefReads.back().first;
|
|
|
|
OpIdx = UndefReads.back().second;
|
|
|
|
}
|
|
|
|
}
|
2011-11-08 05:40:27 +08:00
|
|
|
}
|
|
|
|
|
2010-03-30 07:24:21 +08:00
|
|
|
// A hard instruction only works in one domain. All input registers will be
|
|
|
|
// forced into that domain.
|
2011-09-28 08:01:56 +08:00
|
|
|
void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
|
2010-03-30 07:24:21 +08:00
|
|
|
// Collapse all uses.
|
|
|
|
for (unsigned i = mi->getDesc().getNumDefs(),
|
|
|
|
e = mi->getDesc().getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &mo = mi->getOperand(i);
|
|
|
|
if (!mo.isReg()) continue;
|
2015-03-07 02:56:20 +08:00
|
|
|
for (int rx : regIndices(mo.getReg())) {
|
2014-12-18 03:13:47 +08:00
|
|
|
force(rx, domain);
|
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Kill all defs and force them.
|
|
|
|
for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
|
|
|
|
MachineOperand &mo = mi->getOperand(i);
|
|
|
|
if (!mo.isReg()) continue;
|
2015-03-07 02:56:20 +08:00
|
|
|
for (int rx : regIndices(mo.getReg())) {
|
2014-12-18 03:13:47 +08:00
|
|
|
kill(rx);
|
|
|
|
force(rx, domain);
|
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// A soft instruction can be changed to work in other domains given by mask.
|
2011-09-28 08:01:56 +08:00
|
|
|
void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
|
2010-04-05 05:27:26 +08:00
|
|
|
// Bitmask of available domains for this instruction after taking collapsed
|
|
|
|
// operands into account.
|
|
|
|
unsigned available = mask;
|
|
|
|
|
2010-03-30 07:24:21 +08:00
|
|
|
// Scan the explicit use operands for incoming domains.
|
|
|
|
SmallVector<int, 4> used;
|
2010-03-31 04:04:01 +08:00
|
|
|
if (LiveRegs)
|
|
|
|
for (unsigned i = mi->getDesc().getNumDefs(),
|
|
|
|
e = mi->getDesc().getNumOperands(); i != e; ++i) {
|
2010-04-01 04:32:51 +08:00
|
|
|
MachineOperand &mo = mi->getOperand(i);
|
|
|
|
if (!mo.isReg()) continue;
|
2015-03-07 02:56:20 +08:00
|
|
|
for (int rx : regIndices(mo.getReg())) {
|
2014-12-18 03:13:47 +08:00
|
|
|
DomainValue *dv = LiveRegs[rx].Value;
|
|
|
|
if (dv == nullptr)
|
|
|
|
continue;
|
2010-04-05 05:27:26 +08:00
|
|
|
// Bitmask of domains that dv and available have in common.
|
|
|
|
unsigned common = dv->getCommonDomains(available);
|
2010-04-01 04:32:51 +08:00
|
|
|
// Is it possible to use this collapsed register for free?
|
2010-04-05 05:27:26 +08:00
|
|
|
if (dv->isCollapsed()) {
|
|
|
|
// Restrict available domains to the ones in common with the operand.
|
2013-10-15 06:19:03 +08:00
|
|
|
// If there are no common domains, we must pay the cross-domain
|
2010-04-05 05:27:26 +08:00
|
|
|
// penalty for this operand.
|
|
|
|
if (common) available = common;
|
|
|
|
} else if (common)
|
|
|
|
// Open DomainValue is compatible, save it for merging.
|
2010-04-01 04:32:51 +08:00
|
|
|
used.push_back(rx);
|
|
|
|
else
|
2010-04-05 05:27:26 +08:00
|
|
|
// Open DomainValue is not compatible with instruction. It is useless
|
|
|
|
// now.
|
2011-11-09 05:57:47 +08:00
|
|
|
kill(rx);
|
2010-04-01 04:32:51 +08:00
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// If the collapsed operands force a single domain, propagate the collapse.
|
2010-04-05 05:27:26 +08:00
|
|
|
if (isPowerOf2_32(available)) {
|
2013-05-25 06:23:49 +08:00
|
|
|
unsigned domain = countTrailingZeros(available);
|
2016-06-30 08:01:54 +08:00
|
|
|
TII->setExecutionDomain(*mi, domain);
|
2010-03-30 07:24:21 +08:00
|
|
|
visitHardInstr(mi, domain);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-04-05 05:27:26 +08:00
|
|
|
// Kill off any remaining uses that don't match available, and build a list of
|
|
|
|
// incoming DomainValues that we want to merge.
|
2011-11-15 09:15:25 +08:00
|
|
|
SmallVector<LiveReg, 4> Regs;
|
2013-07-03 13:11:49 +08:00
|
|
|
for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
|
2010-03-30 07:24:21 +08:00
|
|
|
int rx = *i;
|
2014-12-16 02:48:43 +08:00
|
|
|
assert(LiveRegs && "no space allocated for live registers");
|
2011-11-15 09:15:25 +08:00
|
|
|
const LiveReg &LR = LiveRegs[rx];
|
2010-03-31 04:04:01 +08:00
|
|
|
// This useless DomainValue could have been missed above.
|
2011-11-15 09:15:25 +08:00
|
|
|
if (!LR.Value->getCommonDomains(available)) {
|
|
|
|
kill(rx);
|
2010-03-30 07:24:21 +08:00
|
|
|
continue;
|
|
|
|
}
|
2011-11-15 09:15:25 +08:00
|
|
|
// Sorted insertion.
|
|
|
|
bool Inserted = false;
|
2013-07-03 13:11:49 +08:00
|
|
|
for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
|
2011-11-15 09:15:25 +08:00
|
|
|
i != e && !Inserted; ++i) {
|
|
|
|
if (LR.Def < i->Def) {
|
|
|
|
Inserted = true;
|
|
|
|
Regs.insert(i, LR);
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
}
|
2011-11-15 09:15:25 +08:00
|
|
|
if (!Inserted)
|
|
|
|
Regs.push_back(LR);
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
2010-04-05 05:27:26 +08:00
|
|
|
// doms are now sorted in order of appearance. Try to merge them all, giving
|
|
|
|
// priority to the latest ones.
|
2014-04-14 08:51:57 +08:00
|
|
|
DomainValue *dv = nullptr;
|
2011-11-15 09:15:25 +08:00
|
|
|
while (!Regs.empty()) {
|
2010-04-01 04:32:51 +08:00
|
|
|
if (!dv) {
|
2011-11-15 09:15:25 +08:00
|
|
|
dv = Regs.pop_back_val().Value;
|
2011-11-23 12:03:08 +08:00
|
|
|
// Force the first dv to match the current instruction.
|
|
|
|
dv->AvailableDomains = dv->getCommonDomains(available);
|
|
|
|
assert(dv->AvailableDomains && "Domain should have been filtered");
|
2010-04-01 04:32:51 +08:00
|
|
|
continue;
|
|
|
|
}
|
2010-04-05 02:00:21 +08:00
|
|
|
|
2011-11-15 09:15:25 +08:00
|
|
|
DomainValue *Latest = Regs.pop_back_val().Value;
|
|
|
|
// Skip already merged values.
|
|
|
|
if (Latest == dv || Latest->Next)
|
|
|
|
continue;
|
|
|
|
if (merge(dv, Latest))
|
|
|
|
continue;
|
2010-04-05 02:00:21 +08:00
|
|
|
|
2010-04-05 05:27:26 +08:00
|
|
|
// If latest didn't merge, it is useless now. Kill all registers using it.
|
2014-12-16 02:48:43 +08:00
|
|
|
for (int i : used) {
|
|
|
|
assert(LiveRegs && "no space allocated for live registers");
|
|
|
|
if (LiveRegs[i].Value == Latest)
|
|
|
|
kill(i);
|
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// dv is the DomainValue we are going to use for this instruction.
|
2011-11-23 12:03:08 +08:00
|
|
|
if (!dv) {
|
2011-11-09 05:57:47 +08:00
|
|
|
dv = alloc();
|
2011-11-23 12:03:08 +08:00
|
|
|
dv->AvailableDomains = available;
|
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
dv->Instrs.push_back(mi);
|
|
|
|
|
2012-10-03 16:29:36 +08:00
|
|
|
// Finally set all defs and non-collapsed uses to dv. We must iterate through
|
|
|
|
// all the operators, including imp-def ones.
|
|
|
|
for (MachineInstr::mop_iterator ii = mi->operands_begin(),
|
|
|
|
ee = mi->operands_end();
|
|
|
|
ii != ee; ++ii) {
|
|
|
|
MachineOperand &mo = *ii;
|
2010-03-30 07:24:21 +08:00
|
|
|
if (!mo.isReg()) continue;
|
2015-03-07 02:56:20 +08:00
|
|
|
for (int rx : regIndices(mo.getReg())) {
|
2014-12-18 03:13:47 +08:00
|
|
|
if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
|
|
|
|
kill(rx);
|
|
|
|
setLiveReg(rx, dv);
|
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-09-28 08:01:56 +08:00
|
|
|
bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
|
2016-05-04 06:32:30 +08:00
|
|
|
if (skipFunction(*mf.getFunction()))
|
|
|
|
return false;
|
2010-03-26 01:25:00 +08:00
|
|
|
MF = &mf;
|
2014-08-05 10:39:49 +08:00
|
|
|
TII = MF->getSubtarget().getInstrInfo();
|
|
|
|
TRI = MF->getSubtarget().getRegisterInfo();
|
2016-08-18 03:07:40 +08:00
|
|
|
RegClassInfo.runOnMachineFunction(mf);
|
2014-04-14 08:51:57 +08:00
|
|
|
LiveRegs = nullptr;
|
2011-09-28 07:50:46 +08:00
|
|
|
assert(NumRegs == RC->getNumRegs() && "Bad regclass");
|
2010-03-26 01:25:00 +08:00
|
|
|
|
2011-11-15 09:15:25 +08:00
|
|
|
DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
|
2014-11-17 13:50:14 +08:00
|
|
|
<< TRI->getRegClassName(RC) << " **********\n");
|
2011-11-15 09:15:25 +08:00
|
|
|
|
2011-09-28 08:01:56 +08:00
|
|
|
// If no relevant registers are used in the function, we can skip it
|
|
|
|
// completely.
|
2010-03-30 07:24:21 +08:00
|
|
|
bool anyregs = false;
|
2015-07-15 01:52:07 +08:00
|
|
|
const MachineRegisterInfo &MRI = mf.getRegInfo();
|
2015-08-19 02:54:27 +08:00
|
|
|
for (unsigned Reg : *RC) {
|
|
|
|
if (MRI.isPhysRegUsed(Reg)) {
|
|
|
|
anyregs = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
if (!anyregs) return false;
|
2010-03-26 01:25:00 +08:00
|
|
|
|
2011-09-28 07:50:46 +08:00
|
|
|
// Initialize the AliasMap on the first use.
|
|
|
|
if (AliasMap.empty()) {
|
2014-12-18 03:13:47 +08:00
|
|
|
// Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
|
|
|
|
// therefore the LiveRegs array.
|
|
|
|
AliasMap.resize(TRI->getNumRegs());
|
2011-09-28 07:50:46 +08:00
|
|
|
for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
|
2012-06-02 07:28:30 +08:00
|
|
|
for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
|
|
|
|
AI.isValid(); ++AI)
|
2014-12-18 03:13:47 +08:00
|
|
|
AliasMap[*AI].push_back(i);
|
2011-09-28 07:50:46 +08:00
|
|
|
}
|
|
|
|
|
2015-10-10 00:54:49 +08:00
|
|
|
MachineBasicBlock *Entry = &*MF->begin();
|
2011-11-08 05:59:29 +08:00
|
|
|
ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
|
2011-11-09 09:06:56 +08:00
|
|
|
SmallVector<MachineBasicBlock*, 16> Loops;
|
2011-11-08 05:59:29 +08:00
|
|
|
for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
|
|
|
|
MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
|
|
|
|
MachineBasicBlock *MBB = *MBBI;
|
2011-11-15 09:15:25 +08:00
|
|
|
enterBasicBlock(MBB);
|
|
|
|
if (SeenUnknownBackEdge)
|
2011-11-09 09:06:56 +08:00
|
|
|
Loops.push_back(MBB);
|
2015-12-30 01:15:22 +08:00
|
|
|
for (MachineInstr &MI : *MBB)
|
|
|
|
visitInstr(&MI);
|
2013-10-15 06:19:03 +08:00
|
|
|
processUndefReads(MBB);
|
2011-11-08 05:40:27 +08:00
|
|
|
leaveBasicBlock(MBB);
|
2010-03-26 01:25:00 +08:00
|
|
|
}
|
2010-03-30 07:24:21 +08:00
|
|
|
|
2011-11-09 09:06:56 +08:00
|
|
|
// Visit all the loop blocks again in order to merge DomainValues from
|
|
|
|
// back-edges.
|
2015-12-30 01:15:22 +08:00
|
|
|
for (MachineBasicBlock *MBB : Loops) {
|
2011-11-09 09:06:56 +08:00
|
|
|
enterBasicBlock(MBB);
|
2015-12-30 01:15:22 +08:00
|
|
|
for (MachineInstr &MI : *MBB)
|
|
|
|
if (!MI.isDebugValue())
|
|
|
|
processDefs(&MI, false);
|
2013-10-15 06:19:03 +08:00
|
|
|
processUndefReads(MBB);
|
2011-11-09 09:06:56 +08:00
|
|
|
leaveBasicBlock(MBB);
|
|
|
|
}
|
|
|
|
|
2011-11-08 07:08:21 +08:00
|
|
|
// Clear the LiveOuts vectors and collapse any remaining DomainValues.
|
|
|
|
for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
|
|
|
|
MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
|
|
|
|
LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI);
|
2011-11-09 09:06:56 +08:00
|
|
|
if (FI == LiveOuts.end() || !FI->second)
|
2011-11-08 07:08:21 +08:00
|
|
|
continue;
|
|
|
|
for (unsigned i = 0, e = NumRegs; i != e; ++i)
|
2011-11-15 09:15:25 +08:00
|
|
|
if (FI->second[i].Value)
|
|
|
|
release(FI->second[i].Value);
|
2011-11-09 06:05:17 +08:00
|
|
|
delete[] FI->second;
|
2011-11-08 07:08:21 +08:00
|
|
|
}
|
2010-03-31 04:04:01 +08:00
|
|
|
LiveOuts.clear();
|
2013-10-15 06:19:03 +08:00
|
|
|
UndefReads.clear();
|
2010-04-05 02:00:21 +08:00
|
|
|
Avail.clear();
|
|
|
|
Allocator.DestroyAll();
|
2010-03-30 07:24:21 +08:00
|
|
|
|
2010-03-26 01:25:00 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-09-28 07:50:46 +08:00
|
|
|
FunctionPass *
|
|
|
|
llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
|
2011-09-28 08:01:56 +08:00
|
|
|
return new ExeDepsFix(RC);
|
2010-03-26 01:25:00 +08:00
|
|
|
}
|