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[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -instcombine -S | FileCheck %s
; If we have some pattern that leaves only some low bits set, and then performs
; left-shift of those bits, if none of the bits that are left after the final
; shift are modified by the mask, we can omit the mask.
; There are many variants to this pattern:
; f) ((x << maskNbits) a>> maskNbits) << shiftNbits
; simplify to:
; x << shiftNbits
; iff (shiftNbits-maskNbits) s>= 0 (i.e. shiftNbits u>= maskNbits)
; Simple tests. We don't care about extra uses.
declare void @use32(i32)
define i32 @t0_basic(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t0_basic(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X]], [[NBITS]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
call void @use32(i32 %t0)
call void @use32(i32 %t1)
%t2 = shl i32 %t1, %nbits
ret i32 %t2
}
define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t1_bigger_shift(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], 1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[X]], [[T2]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
%t2 = add i32 %nbits, 1
call void @use32(i32 %t0)
call void @use32(i32 %t1)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2
ret i32 %t3
}
; Vectors
declare void @use3xi32(<3 x i32>)
define <3 x i32> @t2_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
; CHECK-LABEL: @t2_vec_splat(
; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1>
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[X]], [[T2]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t0 = shl <3 x i32> %x, %nbits
%t1 = ashr <3 x i32> %t0, %nbits
%t2 = add <3 x i32> %nbits, <i32 1, i32 1, i32 1>
call void @use3xi32(<3 x i32> %t0)
call void @use3xi32(<3 x i32> %t1)
call void @use3xi32(<3 x i32> %t2)
%t3 = shl <3 x i32> %t1, %t2
ret <3 x i32> %t3
}
define <3 x i32> @t3_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
; CHECK-LABEL: @t3_vec_nonsplat(
; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 0, i32 2>
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[X]], [[T2]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t0 = shl <3 x i32> %x, %nbits
%t1 = ashr <3 x i32> %t0, %nbits
%t2 = add <3 x i32> %nbits, <i32 1, i32 0, i32 2>
call void @use3xi32(<3 x i32> %t0)
call void @use3xi32(<3 x i32> %t1)
call void @use3xi32(<3 x i32> %t2)
%t3 = shl <3 x i32> %t1, %t2
ret <3 x i32> %t3
}
define <3 x i32> @t4_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
; CHECK-LABEL: @t4_vec_undef(
; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 undef, i32 1>
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[X]], [[T2]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t0 = shl <3 x i32> %x, %nbits
%t1 = ashr <3 x i32> %t0, %nbits
%t2 = add <3 x i32> %nbits, <i32 1, i32 undef, i32 1>
call void @use3xi32(<3 x i32> %t0)
call void @use3xi32(<3 x i32> %t1)
call void @use3xi32(<3 x i32> %t2)
%t3 = shl <3 x i32> %t1, %t2
ret <3 x i32> %t3
}
; Fast-math flags. We must not preserve them!
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
define i32 @t5_nuw(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t5_nuw(
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X]], [[NBITS]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
call void @use32(i32 %t0)
call void @use32(i32 %t1)
%t2 = shl nuw i32 %t1, %nbits
ret i32 %t2
}
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
define i32 @t6_nsw(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t6_nsw(
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X]], [[NBITS]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
call void @use32(i32 %t0)
call void @use32(i32 %t1)
%t2 = shl nsw i32 %t1, %nbits
ret i32 %t2
}
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
define i32 @t7_nuw_nsw(i32 %x, i32 %nbits) {
; CHECK-LABEL: @t7_nuw_nsw(
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
[InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563) Summary: If we have some pattern that leaves only some low bits set, and then performs left-shift of those bits, if none of the bits that are left after the final shift are modified by the mask, we can omit the mask. There are many variants to this pattern: f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt` All these patterns can be simplified to just: `x << ShiftShAmt` iff: f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`) Normally, the inner pattern is sign-extend, but for our purposes it's no different to other patterns: alive proofs: f: https://rise4fun.com/Alive/7U3 For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 Differential Revision: https://reviews.llvm.org/D64524 llvm-svn: 366540
2019-07-19 16:26:58 +08:00
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X]], [[NBITS]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
call void @use32(i32 %t0)
call void @use32(i32 %t1)
%t2 = shl nuw nsw i32 %t1, %nbits
ret i32 %t2
}
[NFC][InstCombine] Redundant masking before left-shift: tests with assume If the legality check is `(shiftNbits-maskNbits) s>= 0`, then we can simplify it to `shiftNbits u>= maskNbits`, which is easier to check for. However, currently switching the `dropRedundantMaskingOfLeftShiftInput()` to `SimplifyICmpInst()` does not catch these cases and regresses currently-handled cases, so i'll leave it as is for now. https://rise4fun.com/Alive/25P llvm-svn: 366564
2019-07-19 19:29:04 +08:00
; Special test
declare void @llvm.assume(i1 %cond)
; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
; CHECK-LABEL: @t8_assume_uge(
; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[MASKNBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
; CHECK-NEXT: ret i32 [[T2]]
;
%cmp = icmp uge i32 %shiftnbits, %masknbits
call void @llvm.assume(i1 %cmp)
%t0 = shl i32 %x, %masknbits
%t1 = ashr i32 %t0, %masknbits
call void @use32(i32 %t0)
call void @use32(i32 %t1)
%t2 = shl i32 %t1, %shiftnbits
ret i32 %t2
}
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; Negative tests
[NFC][InstCombine] Redundant masking before left-shift: tests with assume If the legality check is `(shiftNbits-maskNbits) s>= 0`, then we can simplify it to `shiftNbits u>= maskNbits`, which is easier to check for. However, currently switching the `dropRedundantMaskingOfLeftShiftInput()` to `SimplifyICmpInst()` does not catch these cases and regresses currently-handled cases, so i'll leave it as is for now. https://rise4fun.com/Alive/25P llvm-svn: 366564
2019-07-19 19:29:04 +08:00
define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
; CHECK-LABEL: @n9_different_shamts0(
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS0]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: ret i32 [[T2]]
;
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
%t0 = shl i32 %x, %nbits0 ; different shift amts
%t1 = ashr i32 %t0, %nbits1 ; different shift amts
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
call void @use32(i32 %t0)
call void @use32(i32 %t1)
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
%t2 = shl i32 %t1, %nbits0
ret i32 %t2
}
[NFC][InstCombine] Redundant masking before left-shift: tests with assume If the legality check is `(shiftNbits-maskNbits) s>= 0`, then we can simplify it to `shiftNbits u>= maskNbits`, which is easier to check for. However, currently switching the `dropRedundantMaskingOfLeftShiftInput()` to `SimplifyICmpInst()` does not catch these cases and regresses currently-handled cases, so i'll leave it as is for now. https://rise4fun.com/Alive/25P llvm-svn: 366564
2019-07-19 19:29:04 +08:00
define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
; CHECK-LABEL: @n10_different_shamts1(
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more llvm-svn: 365694
2019-07-11 03:58:13 +08:00
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS1]]
; CHECK-NEXT: ret i32 [[T2]]
;
%t0 = shl i32 %x, %nbits0 ; different shift amts
%t1 = ashr i32 %t0, %nbits1 ; different shift amts
call void @use32(i32 %t0)
call void @use32(i32 %t1)
%t2 = shl i32 %t1, %nbits1
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
ret i32 %t2
}
[NFC][InstCombine] Redundant masking before left-shift: tests with assume If the legality check is `(shiftNbits-maskNbits) s>= 0`, then we can simplify it to `shiftNbits u>= maskNbits`, which is easier to check for. However, currently switching the `dropRedundantMaskingOfLeftShiftInput()` to `SimplifyICmpInst()` does not catch these cases and regresses currently-handled cases, so i'll leave it as is for now. https://rise4fun.com/Alive/25P llvm-svn: 366564
2019-07-19 19:29:04 +08:00
define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
; CHECK-LABEL: @n11_shamt_is_smaller(
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
[NFC][InstCombine] More tests for PR42563 "Dropping pointless masking before left shift" For patterns c/d/e we too can deal with the pattern even if we can't just drop the mask, we can just apply it afterwars: https://rise4fun.com/Alive/gslRa llvm-svn: 372244
2019-09-19 02:38:32 +08:00
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
; CHECK-NEXT: ret i32 [[T3]]
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
;
%t0 = shl i32 %x, %nbits
%t1 = ashr i32 %t0, %nbits
%t2 = add i32 %nbits, -1
call void @use32(i32 %t0)
call void @use32(i32 %t2)
%t3 = shl i32 %t1, %t2 ; shift is smaller than mask
[NFC][InstCombine] More tests for PR42563 "Dropping pointless masking before left shift" For patterns c/d/e we too can deal with the pattern even if we can't just drop the mask, we can just apply it afterwars: https://rise4fun.com/Alive/gslRa llvm-svn: 372244
2019-09-19 02:38:32 +08:00
ret i32 %t3
[NFC][InstCombine] Redundant masking before left-shift (PR42563) alive proofs: a,b: https://rise4fun.com/Alive/4zsf c,d,e,f: https://rise4fun.com/Alive/RC49 Indeed, not all of these patterns are canonical. But since this fold will only produce a single instruction i'm really interested in handling even uncanonical patterns. Other than these 6 patterns, i can't think of any other reasonable variants right now, although i'm sure they exist. For now let's start with patterns where both shift amounts are variable, with trivial constant "offset" between them, since i believe this is both simplest to handle and i think this is most common. But again, there are likely other variants where we could use ValueTracking/ConstantRange to handle more cases. https://bugs.llvm.org/show_bug.cgi?id=42563 llvm-svn: 365641
2019-07-10 23:08:06 +08:00
}