Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/*===------------ avx512bf16intrin.h - AVX512_BF16 intrinsics --------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <avx512bf16intrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __AVX512BF16INTRIN_H
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#define __AVX512BF16INTRIN_H
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typedef short __m512bh __attribute__((__vector_size__(64), __aligned__(64)));
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typedef short __m256bh __attribute__((__vector_size__(32), __aligned__(32)));
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#define __DEFAULT_FN_ATTRS512 \
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__attribute__((__always_inline__, __nodebug__, __target__("avx512bf16"), \
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__min_vector_width__(512)))
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [16 x float].
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/// \param __B
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/// A 512-bit vector of [16 x float].
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/// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 256 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m512bh __DEFAULT_FN_ATTRS512
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_mm512_cvtne2ps_pbh(__m512 __A, __m512 __B) {
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return (__m512bh)__builtin_ia32_cvtne2ps2bf16_512((__v16sf) __A,
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(__v16sf) __B);
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [16 x float].
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/// \param __B
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/// A 512-bit vector of [16 x float].
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/// \param __W
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/// A 512-bit vector of [32 x bfloat].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 32-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A or __B. A 0 means element from __W.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 256 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m512bh __DEFAULT_FN_ATTRS512
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_mm512_mask_cvtne2ps_pbh(__m512bh __W, __mmask32 __U, __m512 __A, __m512 __B) {
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return (__m512bh)__builtin_ia32_selectw_512((__mmask32)__U,
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(__v32hi)_mm512_cvtne2ps_pbh(__A, __B),
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(__v32hi)__W);
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}
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/// Convert Two Packed Single Data to One Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [16 x float].
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/// \param __B
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/// A 512-bit vector of [16 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 32-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A or __B. A 0 means element is zero.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
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2019-05-17 01:34:35 +08:00
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/// conversion of __B, and higher 256 bits come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m512bh __DEFAULT_FN_ATTRS512
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_mm512_maskz_cvtne2ps_pbh(__mmask32 __U, __m512 __A, __m512 __B) {
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return (__m512bh)__builtin_ia32_selectw_512((__mmask32)__U,
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(__v32hi)_mm512_cvtne2ps_pbh(__A, __B),
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(__v32hi)_mm512_setzero_si512());
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [16 x float].
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2019-05-17 01:34:35 +08:00
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/// \returns A 256-bit vector of [16 x bfloat] come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m256bh __DEFAULT_FN_ATTRS512
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_mm512_cvtneps_pbh(__m512 __A) {
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2019-05-17 02:28:17 +08:00
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return (__m256bh)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
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(__v16hi)_mm256_undefined_si256(),
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(__mmask16)-1);
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [16 x float].
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/// \param __W
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/// A 256-bit vector of [16 x bfloat].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A. A 0 means element from __W.
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/// \returns A 256-bit vector of [16 x bfloat] come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m256bh __DEFAULT_FN_ATTRS512
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_mm512_mask_cvtneps_pbh(__m256bh __W, __mmask16 __U, __m512 __A) {
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2019-05-17 02:28:17 +08:00
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return (__m256bh)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
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(__v16hi)__W,
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(__mmask16)__U);
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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}
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/// Convert Packed Single Data to Packed BF16 Data.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [16 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means conversion of __A. A 0 means element is zero.
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/// \returns A 256-bit vector of [16 x bfloat] come from conversion of __A.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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static __inline__ __m256bh __DEFAULT_FN_ATTRS512
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_mm512_maskz_cvtneps_pbh(__mmask16 __U, __m512 __A) {
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2019-05-17 02:28:17 +08:00
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return (__m256bh)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
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(__v16hi)_mm256_setzero_si256(),
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(__mmask16)__U);
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [32 x bfloat].
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/// \param __B
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/// A 512-bit vector of [32 x bfloat].
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/// \param __D
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/// A 512-bit vector of [16 x float].
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/// \returns A 512-bit vector of [16 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m512 __DEFAULT_FN_ATTRS512
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_mm512_dpbf16_ps(__m512 __D, __m512bh __A, __m512bh __B) {
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return (__m512)__builtin_ia32_dpbf16ps_512((__v16sf) __D,
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(__v16si) __A,
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(__v16si) __B);
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [32 x bfloat].
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/// \param __B
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/// A 512-bit vector of [32 x bfloat].
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/// \param __D
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/// A 512-bit vector of [16 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means __A and __B's dot product accumulated with __D. A 0 means __D.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 512-bit vector of [16 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m512 __DEFAULT_FN_ATTRS512
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_mm512_mask_dpbf16_ps(__m512 __D, __mmask16 __U, __m512bh __A, __m512bh __B) {
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return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
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(__v16sf)_mm512_dpbf16_ps(__D, __A, __B),
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(__v16sf)__D);
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}
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/// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
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///
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/// \param __A
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/// A 512-bit vector of [32 x bfloat].
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/// \param __B
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/// A 512-bit vector of [32 x bfloat].
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/// \param __D
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/// A 512-bit vector of [16 x float].
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/// \param __U
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2019-05-17 01:34:35 +08:00
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/// A 16-bit mask value specifying what is chosen for each element.
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/// A 1 means __A and __B's dot product accumulated with __D. A 0 means 0.
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Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Patch by LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60552
llvm-svn: 360018
2019-05-06 16:25:11 +08:00
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/// \returns A 512-bit vector of [16 x float] comes from Dot Product of
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/// __A, __B and __D
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static __inline__ __m512 __DEFAULT_FN_ATTRS512
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_mm512_maskz_dpbf16_ps(__mmask16 __U, __m512 __D, __m512bh __A, __m512bh __B) {
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return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
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(__v16sf)_mm512_dpbf16_ps(__D, __A, __B),
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(__v16sf)_mm512_setzero_si512());
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}
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#undef __DEFAULT_FN_ATTRS512
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#endif
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