forked from OSchip/llvm-project
67 lines
2.0 KiB
LLVM
67 lines
2.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector mask manipulation operations
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; on Power10.
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declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>)
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declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>)
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declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>)
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declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>)
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declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>)
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define i32 @test_vextractbm(<16 x i8> %a) {
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; CHECK-LABEL: test_vextractbm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractbm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractbm(<16 x i8> %a)
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ret i32 %ext
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}
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define i32 @test_vextracthm(<8 x i16> %a) {
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; CHECK-LABEL: test_vextracthm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextracthm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextracthm(<8 x i16> %a)
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ret i32 %ext
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}
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define i32 @test_vextractwm(<4 x i32> %a) {
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; CHECK-LABEL: test_vextractwm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractwm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractwm(<4 x i32> %a)
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ret i32 %ext
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}
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define i32 @test_vextractdm(<2 x i64> %a) {
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; CHECK-LABEL: test_vextractdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractdm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractdm(<2 x i64> %a)
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ret i32 %ext
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}
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define i32 @test_vextractqm(<1 x i128> %a) {
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; CHECK-LABEL: test_vextractqm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractqm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a)
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ret i32 %ext
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}
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