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llvm-project/llvm/test/CodeGen/Hexagon/static.ll

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Disable Hexagon test temporarily. There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617
2012-04-13 05:06:54 +08:00
; RUN: true
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s | FileCheck %s
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
@num = external global i32
@acc = external global i32
@val = external global i32
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
2012-02-02 06:13:57 +08:00
; CHECK: CONST32(#num)
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
; CHECK: CONST32(#acc)
; CHECK: CONST32(#val)
define void @foo() nounwind {
entry:
%0 = load i32* @num, align 4
%1 = load i32* @acc, align 4
%mul = mul nsw i32 %0, %1
%2 = load i32* @val, align 4
%add = add nsw i32 %mul, %2
store i32 %add, i32* @num, align 4
ret void
}