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llvm-project/llvm/test/MC/Disassembler/simple-tests.txt

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specify a triple to use, fixing the test on non-x86-64 hosts. llvm-svn: 91900
2009-12-22 15:01:12 +08:00
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
rewrite the file parser for the disassembler, implementing support for comments. Also, check in a simple testcase for the disassembler, including a test for r91864 llvm-svn: 91894
2009-12-22 14:37:58 +08:00
# CHECK: int $33
0xCD 0x21
# CHECK: int $33
0xCD 0x21
# CHECK: addb %al, (%rax)
various cleanups, make the disassemble reject lines with too much data on them, for example: addb %al, (%rax) simple-tests.txt:11:5: error: excess data detected in input 0 0 0 0 0 ^ llvm-svn: 91896
2009-12-22 14:56:51 +08:00
0 0
rewrite the file parser for the disassembler, implementing support for comments. Also, check in a simple testcase for the disassembler, including a test for r91864 llvm-svn: 91894
2009-12-22 14:37:58 +08:00
# CHECK: callq -1234
0xe8 0x2e 0xfb 0xff 0xff
add some disassemble testcases for weird instructions llvm-svn: 96045
2010-02-13 07:46:48 +08:00
# CHECK: lfence
0x0f 0xae 0xe8
# CHECK: mfence
0x0f 0xae 0xf0
# CHECK: monitor
0x0f 0x01 0xc8
# CHECK: mwait
0x0f 0x01 0xc9
# CHECK: vmcall
0x0f 0x01 0xc1
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs fix swapgs to be spelled right. llvm-svn: 96058
2010-02-13 08:41:14 +08:00
# CHECK: vmlaunch
0x0f 0x01 0xc2
# CHECK: vmresume
0x0f 0x01 0xc3
# CHECK: vmxoff
0x0f 0x01 0xc4
# CHECK: swapgs
add encoder support and tests for rdtscp llvm-svn: 96076
2010-02-13 11:42:24 +08:00
0x0f 0x01 0xf8
# CHECK: rdtscp
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes for the encoding and is not the same as vmptrld. llvm-svn: 97992
2010-03-09 06:17:26 +08:00
0x0f 0x01 0xf9
# CHECK: vmxon
0xf3 0x0f 0xc7 0x30
# CHECK: vmptrld
0x0f 0xc7 0x30
# CHECK: vmptrst
0x0f 0xc7 0x38
testcase for r101538, patch by Nico Schmidt! llvm-svn: 101642
2010-04-18 01:22:06 +08:00
# CHECK: movl $0, -4(%rbp)
0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
Eliminated the classification of control registers into %ecr_ and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
2010-05-07 04:59:00 +08:00
# CHECK: movq %cr0, %rcx
0x0f 0x20 0xc1
my work on adding segment registers to LEA missed the disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. llvm-svn: 108226
2010-07-13 12:23:55 +08:00
# CHECK: leal 4(%rsp), %ecx
0x8d 0x4c 0x24 0x04